公开(公告)号：US08084818B2

公开(公告)日：2011-12-27

申请号：US11332189

申请日：2006-01-12

申请人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinksy

发明人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinksy

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

摘要翻译： 高迁移率半导体组件。 在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。 第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。 在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过 约45度。

公开(公告)号：US20100065888A1

公开(公告)日：2010-03-18

申请号：US11332189

申请日：2006-01-12

申请人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert S. Chau ,  Peter Tolchinksy

发明人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert S. Chau ,  Peter Tolchinksy

IPC分类号： H01L29/778

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

摘要翻译： 高迁移率半导体组件。 在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。 第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。 在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过 约45度。

公开(公告)号：US07042009B2

公开(公告)日：2006-05-09

申请号：US10883183

申请日：2004-06-30

申请人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinsky

发明人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinsky

IPC分类号： H01L27/01 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

摘要翻译： 高迁移率半导体组件。 在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。 第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。 在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过 约45度。

公开(公告)号：US20060001109A1

公开(公告)日：2006-01-05

申请号：US10883183

申请日：2004-06-30

申请人： Mohamad Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert Chau ,  Peter Tolchinksy

发明人： Mohamad Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert Chau ,  Peter Tolchinksy

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

公开(公告)号：US08980650B2

公开(公告)日：2015-03-17

申请号：US14454682

申请日：2014-08-07

申请人： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

发明人： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L29/82 ,  H01L27/22 ,  H01L43/10 ,  H01F10/32 ,  H01F10/193 ,  G11C11/16

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

摘要翻译： 适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。 在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

公开(公告)号：US08836056B2

公开(公告)日：2014-09-16

申请号：US13627968

申请日：2012-09-26

申请人： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

发明人： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

IPC分类号： H01L29/32 ,  H01L43/12

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

摘要翻译： 适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。 在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

公开(公告)号：US20120012934A1

公开(公告)日：2012-01-19

申请号：US13243441

申请日：2011-09-23

申请人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

公开(公告)号：US20100155848A1

公开(公告)日：2010-06-24

申请号：US12317536

申请日：2008-12-24

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian Doyle ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian Doyle ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L27/1104 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211

摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.

摘要翻译： 静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分 地区。 静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。 实现静态随机存取存储器电路的过程包括源极和漏极外延。

公开(公告)号：US07666727B2

公开(公告)日：2010-02-23

申请号：US11099190

申请日：2005-04-04

申请人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

发明人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/32051 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

摘要翻译： 一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。 在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。 栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述 一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

公开(公告)号：US07170120B2

公开(公告)日：2007-01-30

申请号：US11096984

申请日：2005-03-31

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/76

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.