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    Multi-chip package structure
    1.
    发明授权
    Multi-chip package structure 有权
    多芯片封装结构

    公开(公告)号：US07151317B2

    公开(公告)日：2006-12-19

    申请号：US10904404

    申请日：2004-11-09

    申请人： Shin-Hua Chao ,  Jian-Wen Lo

    发明人： Shin-Hua Chao ,  Jian-Wen Lo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

    摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

    摘要翻译： 提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。 第一芯片具有第一活性表面。 图案化层压层设置在第一活性表面的一部分区域上。 第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。 第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。 第二芯片通过第一凸块电连接到第一焊盘。 第二凸块设置在第二接合焊盘上。 此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

    Process for testing IC wafer
    5.
    发明申请
    Process for testing IC wafer 审中-公开
    IC晶圆测试工艺

    公开(公告)号：US20050019965A1

    公开(公告)日：2005-01-27

    申请号：US10895061

    申请日：2004-07-21

    申请人： Shin-Hua Chao ,  Yao-Hsin Feng

    发明人： Shin-Hua Chao ,  Yao-Hsin Feng

    IPC分类号： G01R31/28 ,  H01L21/301 ,  H01L23/58

    CPC分类号： H01L22/32 ,  G01R31/2831 ,  G01R31/2856

    摘要： A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing. And the testing step can obtain the influence of side chipping on the chips

    摘要翻译： 公开了一种用于测试IC晶片的方法。 在晶片上的芯片电气测试之前，预先切割晶片以形成与晶片的有效表面上的划线对准的多个凹槽。 在完成芯片的电气或可靠性测试之后，进行单晶化步骤以形成多个独立的芯片。 由于预切割步骤，芯片仍然集成在晶圆上以进行准确的探测和测试。 并且测试步骤可以获得芯片边缘切片的影响

    Semiconductor chip package and manufacturing method thereof
    6.
    发明授权
    Semiconductor chip package and manufacturing method thereof 有权
    半导体芯片封装及其制造方法

    公开(公告)号：US06348729B1

    公开(公告)日：2002-02-19

    申请号：US09390695

    申请日：1999-09-07

    申请人： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

    发明人： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

    IPC分类号： H01L2352

    CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

    摘要翻译： 半导体芯片封装通常包括引线框架，半导体管芯和塑料封装体。 引线框架包括多个引线和窗垫。 窗垫通过连接杆连接到引线框架。 多个引线的内端限定中心区域。 窗垫设置在中心区域中并且具有限定在其中的开口。 半导体管芯设置在窗垫的开口中，并且在其活性表面上形成有多个接合焊盘。 引线的内端通过多根接合线与半导体管芯上的焊盘相互连接。 引线框架，半导体管芯和接合线被封装在塑料封装主体中，其中引线框架的下表面和半导体管芯的后表面通过塑料封装主体露出。

    Stackable Package Having Embedded Interposer and Method for Making the Same
    8.
    发明申请
    Stackable Package Having Embedded Interposer and Method for Making the Same 审中-公开
    具有嵌入式内插器的可堆叠封装及其制作方法

    公开(公告)号：US20100289133A1

    公开(公告)日：2010-11-18

    申请号：US12727770

    申请日：2010-03-19

    申请人： Shin-Hua Chao ,  Teck-Chong Lee ,  Shing-Cheng Liang

    发明人： Shin-Hua Chao ,  Teck-Chong Lee ,  Shing-Cheng Liang

    IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L23/498

    CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad. The solder mask is disposed adjacent to the circuit layer, and exposes the pad. Therefore, the package has more pads for inputting/outputting, more flexibility for stacking a top package, and a reduced total thickness.

    摘要翻译： 本发明涉及具有嵌入式插入器的可堆叠封装及其制造方法。 封装包括衬底，芯片，第一嵌入式插入器，电路层和焊接掩模。 基板具有上表面，底表面和至少一个连接垫。 连接垫邻近上表面设置。 芯片靠近基板的上表面设置，并与基板电连接。 第一嵌入式插入器封装衬底和芯片的上表面。 第一嵌入式插入器包括至少一个电镀通孔。 电镀通孔穿过第一嵌入式插入器，并连接到衬底的连接焊盘。 电路层与第一嵌入式插入件相邻设置，电镀通孔与电路层连接。 电路层包括至少一个焊盘。 焊接掩模邻近电路层设置，并露出焊盘。 因此，封装具有更多的用于输入/输出的焊盘，用于堆叠顶部封装的更大的灵活性和更小的总厚度。

    MULTI-CHIP PACKAGE STRUCTURE
    9.
    发明申请
    MULTI-CHIP PACKAGE STRUCTURE 有权
    多芯片包装结构

    公开(公告)号：US20050199991A1

    公开(公告)日：2005-09-15

    申请号：US10904404

    申请日：2004-11-09

    申请人： Shin-Hua Chao ,  Jian-Wen Lo

    发明人： Shin-Hua Chao ,  Jian-Wen Lo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

    摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

    摘要翻译： 提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。 第一芯片具有第一活性表面。 图案化层压层设置在第一活性表面的一部分区域上。 第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。 第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。 第二芯片通过第一凸块电连接到第一焊盘。 第二凸块设置在第二接合焊盘上。 此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

    Method of making ball grid array package
    10.
    发明授权
    Method of making ball grid array package 有权
    制造球栅阵列封装的方法

    公开(公告)号：US06355499B1

    公开(公告)日：2002-03-12

    申请号：US09610859

    申请日：2000-07-06

    申请人： Shyh-Ing Wu ,  Shin Hua Chao ,  Yao Shin Fang

    发明人： Shyh-Ing Wu ,  Shin Hua Chao ,  Yao Shin Fang

    IPC分类号： H01L2144

    CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A method of making a ball grid array package comprises the steps of: (a) providing a film having an opening defined therein; (b) placing the film on a substrate; (c) attaching a semiconductor chip onto the substrate such that the semiconductor chip is positioned in the opening of the film; (d) electrically coupling the semiconductor chip to the substrate; (e) providing a molding die having a runner, a gate and a molding cavity defined therein, wherein the runner is connected to the molding cavity through the gate; (f) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the molding cavity wherein the edges of the molding cavity fit entirely within the opening of the film and the edges of the runners and the gates are entirely positioned against the film; (g) transferring a hardenable molding compound into the molding cavity; (h) hardening the molding compound; (i) unclamping and opening the molding die; and (j) simultaneously removing the film and degating. The film in accordance with the present invention is characterized in that the adhesive force between the film and the molding compound is greater than the adhesive force between the film and the substrate. This makes the film tend to adhere to the excess molding compound; hence, the film will be removed along with the excess molding compound during the step (j) thereby automating the molding process.

    摘要翻译： 制造球栅阵列封装的方法包括以下步骤：（a）提供其中限定有开口的膜; （b）将膜放置在基底上; （c）将半导体芯片附着在基板上，使得半导体芯片位于膜的开口中; （d）将半导体芯片电耦合到基板; （e）提供具有限定在其中的流道，浇口和模制腔的模具，其中流道通过浇口连接到模腔; （f）以半导体芯片定位在模制腔中的方式闭合和夹紧模具，其中模制空腔的边缘完全配合在薄膜的开口内，并且流道和浇口的边缘完全被定位成抵抗 这个电影; （g）将可硬化的模塑料转移到模腔中; （h）硬化模塑料; （i）松开和打开成型模具; 和（j）同时除去膜并脱胶。 根据本发明的膜的特征在于，膜和模塑料之间的粘合力大于膜和基材之间的粘合力。 这使得膜倾向于粘附到多余的模塑料上; 因此，在步骤（j）期间，膜将与多余的模塑料一起被去除，从而使模制过程自动化。