公开(公告)号：US06682975B2

公开(公告)日：2004-01-27

申请号：US10001535

申请日：2001-11-13

申请人： Myeong-cheol Kim ,  Byeong-yun Nam ,  Sang-sup Jeong ,  Tae-hyuk Ahn

发明人： Myeong-cheol Kim ,  Byeong-yun Nam ,  Sang-sup Jeong ,  Tae-hyuk Ahn

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant structure having the bit lines and removing the insulating layer on the bit lines and on the first interlayer dielectric film to form insulating spacers only at both side walls of the bit lines, forming a second interlayer dielectric film on the resultant structure having the insulating spacers and forming a fourth opening self-aligned to the insulating spacers to open the surface of the second pad layer, and filling the fourth opening with a conductive material.

摘要翻译： 提供一种制造具有自对准接触的半导体存储器件的方法，包括以恒定间隔在预定方向上在半导体衬底的有源区上插入栅绝缘层来形成多个栅电极的步骤， 在具有栅电极的所得结构上形成第一绝缘层，然后形成部分地打开半导体衬底的有源区的第一和第二开口中的一个或多个，通过填充第一和第二开口形成第一和第二衬垫层 在第一绝缘层上形成具有第一和第二焊盘层的第一层间电介质膜，并形成第三开口，该第三开口打开第一焊盘层的表面，在与第一绝缘层正交的方向上形成多个位线 同时填充第三开口的第一层间电介质膜上的栅电极，沉积绝缘体 层，并且除去位线上和第一层间电介质膜上的绝缘层，仅在位线的两个侧壁处形成绝缘间隔，在所得结构上形成第二层间电介质膜，具有 绝缘间隔件，并形成与绝缘垫片自对准的第四开口，以打开第二垫层的表面，并用导电材料填充第四开口。

公开(公告)号：US06573551B1

公开(公告)日：2003-06-03

申请号：US09654664

申请日：2000-09-05

申请人： Myeong-cheol Kim ,  Byeong-yun Nam ,  Sang-sup Jeong ,  Tae-hyuk Ahn

发明人： Myeong-cheol Kim ,  Byeong-yun Nam ,  Sang-sup Jeong ,  Tae-hyuk Ahn

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant structure having the bit lines and removing the insulating layer on the bit lines and on the first interlayer dielectric film to form insulating spacers only at both side walls of the bit lines, forming a second interlayer dielectric film on the resultant structure having the insulating spacers and forming a fourth opening self-aligned to the insulating spacers to open the surface of the second pad layer, and filling the fourth opening with a conductive material.

公开(公告)号：US06885052B2

公开(公告)日：2005-04-26

申请号：US09790240

申请日：2001-02-21

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US07132708B2

公开(公告)日：2006-11-07

申请号：US11054593

申请日：2005-02-09

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US20050167758A1

公开(公告)日：2005-08-04

申请号：US11054593

申请日：2005-02-09

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L31/113

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

公开(公告)号：US06690093B2

公开(公告)日：2004-02-10

申请号：US09878944

申请日：2001-06-13

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim

IPC分类号： H01L2348

CPC分类号： H01L21/76885 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film and etching is stopped when barrier metal layers under the metal layer is exposed. Then, after forming spacers on the sidewalls of an upper conductive layer, the barrier metal layers (a barrier layer and an ohmic layer) are removed using the spacers as etching masks. Therefore, it is possible to prevent problems due to etch mask misalignment, such as 1) an etching gas of the metal layer permeating through the ohmic layer and 2) defects such as contact resistance changes that occur when spacers cover a contact hole even though the upper conductive layer does not completely cover that contact hole.

摘要翻译： 半导体器件的金属接触结构及其形成方法，其中通过蚀刻金属层形成上导电层，所述金属层填充接触孔并形成在层间电介质膜的整个表面上，并且蚀刻停止 当金属层下面的阻挡金属层暴露时。 然后，在上导电层的侧壁上形成间隔物之后，使用间隔物作为蚀刻掩模去除阻挡金属层（阻挡层和欧姆层）。 因此，可以防止由于蚀刻掩模未对准引起的问题，例如1）渗透欧姆层的金属层的蚀刻气体，以及2）当间隔物覆盖接触孔时发生的诸如接触电阻变化的缺陷，即使 上导电层不能完全覆盖该接触孔。

公开(公告)号：US09054051B2

公开(公告)日：2015-06-09

申请号：US13473091

申请日：2012-05-16

申请人： Soo-yeon Jeong ,  In-ho Kim ,  Hyung-yong Kim ,  Myeong-cheol Kim

发明人： Soo-yeon Jeong ,  In-ho Kim ,  Hyung-yong Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/311 ,  H01L27/102 ,  H01L49/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76898 ,  H01L27/1021 ,  H01L27/2409 ,  H01L28/91 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

摘要： In a method of fabricating a semiconductor device, a target layer and a first material layer are sequentially formed on a substrate. A plurality of second material layer patterns are formed on the first material layer, the second material layer patterns extending in a first horizontal direction. A plurality of hardmask patterns extending in a second horizontal direction are formed on the plurality of second material layer patterns and the first material layer, wherein the second horizontal direction is different from the first horizontal direction. A first material layer pattern is formed by etching the first material layer using the plurality of hardmask patterns and the plurality of second material layer patterns as etch masks. A target layer pattern with a plurality of holes is formed by etching the target layer using the first material layer pattern as an etch mask.

摘要翻译： 在制造半导体器件的方法中，目标层和第一材料层依次形成在衬底上。 在第一材料层上形成多个第二材料层图案，第二材料层图案沿第一水平方向延伸。 在多个第二材料层图案和第一材料层上形成有沿第二水平方向延伸的多个硬掩模图案，其中第二水平方向与第一水平方向不同。 通过使用多个硬掩模图案和多个第二材料层图案作为蚀刻掩模蚀刻第一材料层来形成第一材料层图案。 通过使用第一材料层图案作为蚀刻掩模蚀刻目标层来形成具有多个孔的目标层图案。

公开(公告)号：US09048192B2

公开(公告)日：2015-06-02

申请号：US13493146

申请日：2012-06-11

申请人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

发明人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

IPC分类号： H01L21/00 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L23/5283 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/32139 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

摘要翻译： 形成图案的方法包括在基板上形成掩模图案; 通过深反应离子蚀刻（DRIE）蚀刻衬底并通过使用掩模图案作为蚀刻掩模; 部分地去除所述掩模图案以暴露所述基板的上表面的一部分; 并蚀刻衬底的上表面的暴露部分。 在该方法中，当由DRIE形成图案时，图案的上部不突出或几乎不突出，并且图案的侧壁的扇形光滑，因此可以容易地在保护层的表面上形成共形材料层 模式。

公开(公告)号：US07601647B2

公开(公告)日：2009-10-13

申请号：US11810200

申请日：2007-06-05

申请人： Kyung-yub Jeon ,  Myeong-cheol Kim ,  Hak-sun Lee

发明人： Kyung-yub Jeon ,  Myeong-cheol Kim ,  Hak-sun Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/32137

摘要： A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.

摘要翻译： 形成半导体器件的精细图案的方法包括通过改变产生聚合物副产物的量来双重蚀刻，以在具有不同图案密度的区域中蚀刻具有不同厚度的膜。 在第一蚀刻中，在第一蚀刻环境下，在低密度图案区域和高密度图案区域中的缓冲层和硬掩模层上执行反应离子蚀刻（RIE），直到蚀刻膜暴露于低 使用掩模图案作为蚀刻掩模的密度图案区域。 在用于形成硬掩模图案的第二蚀刻中，使用掩模图案作为蚀刻掩模，硬掩模层被蚀刻直到蚀刻膜在高密度图案区域中暴露，同时在低密度图案区域中的蚀刻膜上聚集聚合物副产物， 在第二蚀刻环境下具有比在第一蚀刻环境中产生的聚合物副产物大的密度图案区域。

公开(公告)号：US06385020B1

公开(公告)日：2002-05-07

申请号：US09487740

申请日：2000-01-19

申请人： Hyun-bo Shin ,  Myeong-cheol Kim ,  Jin-won Kim ,  Ki-hyun Hwang ,  Jae-young Park ,  Bon-young Koo

发明人： Hyun-bo Shin ,  Myeong-cheol Kim ,  Jin-won Kim ,  Ki-hyun Hwang ,  Jae-young Park ,  Bon-young Koo

IPC分类号： H02H700

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84

摘要： A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.

摘要翻译： 在电容器下电极的表面的至少一部分上具有HSG的半球状晶粒（HSG）电容器及其形成方法。 在电容器中，下电极由至少两个非晶硅层形成，包括掺杂有高浓度杂质的非晶硅层和掺杂有低浓度杂质的非晶硅层，形成HSG， 可以调节半球形颗粒，使得形成在U形下电极的内表面上或堆叠的下电极的顶部上的HSG的尺寸大于形成在U形下电极的外表面上的HSG的尺寸 或在堆叠的下电极的侧面上。 因此，可以通过适当地调节HSG的尺寸来避免相邻的下部电极之间的桥接，导致晶片到晶片和晶片内的均匀电容。 也可以提高U形下电极的机械强度。