公开(公告)号：US20020042164A1

公开(公告)日：2002-04-11

申请号：US09995722

申请日：2001-11-29

Applicant: NEC CORPORATION

Inventor： Takuo Funaya ,  Tadanori Shimoto ,  Naoji Senba ,  Koji Matsui

IPC: H01L021/48

CPC classification number: H05K3/284 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/162 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic device assembly for dense mounting of electronic devices and method of connecting the electronic devices are disclosed. Conductive portions implemented by metal bumps and sealing portions implemented by adhesive seal resin are connected by thermocompress ion at the same time between two electronic devices. This may be repeated between three or more electronic device.

Abstract translation: 公开了一种用于密集安装电子设备的电子设备组件和连接电子设备的方法。 由金属凸块和由粘合密封树脂实现的密封部分实现的导电部分在两个电子器件之间同时通过热压相连。 这可以在三个或更多个电子设备之间重复。

公开(公告)号：US20020020836A1

公开(公告)日：2002-02-21

申请号：US09838337

申请日：2001-04-20

Applicant: NEC Corporation

Inventor： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Akinobu Shibuya

IPC: H01L047/00

CPC classification number: H01L28/55 ,  H01L21/3212 ,  H01L21/76877 ,  H01L28/75 ,  H05K1/162

Abstract: There is provided a thin film capacitor including (a) a lower electrode, (b) an insulating layer formed burying the lower electrode therein and formed with a via-hole reaching the lower electrode, (c) a dielectric layer formed on an inner sidewall of the via-hole and covering an exposed surface of the lower electrode therewith, and (d) an upper electrode surrounded by the dielectric layer. In accordance with the thin film capacitor, the upper electrode is formed to be buried in the via-hole formed above the lower electrode. Hence, it is possible to prevent short-circuit between the upper and lower electrodes, and degradation of the dielectric layer during fabrication of a thin film capacitor, both of which enhances reliability of a capacitor. In addition, a multi-layered wiring structure could be readily fabricated on the thin film capacitor.

Abstract translation: 提供一种薄膜电容器，其包括（a）下电极，（b）在其中埋设下电极并形成有到达下电极的通孔形成的绝缘层，（c）形成在内侧壁上的电介质层 的通孔，并且覆盖下电极的暴露表面，以及（d）由电介质层包围的上电极。 根据薄膜电容器，上电极被形成为埋在形成在下电极上的通孔中。 因此，可以防止上下电极之间的短路，以及薄膜电容器的制造时的电介质层的劣化，这两者都提高了电容器的可靠性。 此外，可以容易地在薄膜电容器上制造多层布线结构。

公开(公告)号：US20040089470A1

公开(公告)日：2004-05-13

申请号：US10701594

申请日：2003-11-06

Applicant: NEC CORPORATION

Inventor： Tadanori Shimoto ,  Hirokazu Honda ,  Keiichiro Kata ,  Hideya Murai ,  Katsumi Kikuchi ,  Kazuhiro Baba

IPC: H05K001/00

CPC classification number: H05K1/0346 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/205 ,  H05K3/386 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2203/0733 ,  H01L2224/0401

Abstract: A printed circuit board is provided including a lower interconnect, a base insulating film formed on the lower interconnect, and a via hole formed on the base insulating film, and an upper interconnect connected to the lower interconnect with the via hole. The base insulating film has a thickness of about 3 to 100 nullm and has a breaking strength of about 80 MPa or more at a temperature of 23null C. and when the base insulating film is defined to have a breaking strength nullanull at a temperature of null65null C. and a breaking strength nullbnull at a temperature of 150null C., a value of a ratio (a/b) is about 4.5 or less.

Abstract translation: 提供一种印刷电路板，包括下互连，形成在下互连上的基绝缘膜，以及形成在基绝缘膜上的通孔，以及与通孔相连的下互连的上互连。 基底绝缘膜的厚度为3〜100μm左右，在23℃的温度下具有约80MPa以上的断裂强度，并且当基底绝缘膜的断裂强度a 温度为-65℃，断裂强度“b”在150℃的温度下，比率（a / b）为4.5以下。

公开(公告)号：US20020024138A1

公开(公告)日：2002-02-28

申请号：US09922766

申请日：2001-08-07

Applicant: NEC Corporation

Inventor： Tadanori Shimoto ,  Koji Matsui ,  Katsumi Kikuchi

IPC: H01L023/48

CPC classification number: H05K3/4673 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/036 ,  H05K3/007 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2203/0152 ,  H05K2203/124 ,  H01L2924/00

Abstract: A wiring board for high dense mounting comprises at least one layer of interlayer insulator and at least one layer of conductive wiring pattern formed on a base material. The interlayer insulator comprises a polybenzoxazole film. An adhesive layer comprising at least one selected from the group consisting of Ti, Ti-containing compounds and Ni is formed between the polybenzoxazole film and the conductive wiring pattern. The wiring board has a high heat resistance, low dielectric constant, low water absorption degree, low thermal expansion coefficient, and high adhesion between conductors and insulators. The wiring board is also excellent in film strength and shear extensibility, capable of enduring a stress in mounting of a semiconductor device, excellent in reliability, and optimal for high speed and high dense mounting.

Abstract translation: 用于高密度安装的布线板包括至少一层层间绝缘体和形成在基材上的至少一层导电布线图案。 层间绝缘体包含聚苯并恶唑膜。 在聚苯并恶唑膜和导电布线图案之间形成包含选自Ti，Ti的化合物和Ni中的至少一种的粘合剂层。 布线板具有高耐热性，低介电常数，低吸水度，低热膨胀系数以及导体和绝缘体之间的高粘合性。 布线板的膜强度和剪切伸长性也优异，能够耐受半导体器件的安装应力，可靠性优异，并且对于高速，高密度安装是最佳的。

公开(公告)号：US20020001937A1

公开(公告)日：2002-01-03

申请号：US09894123

申请日：2001-06-29

Applicant: NEC CORPORATION

Inventor： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Kazuhiro Baba

IPC: H01L021/4763

CPC classification number: H01L21/4857 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/44 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/0376 ,  H05K2203/061 ,  H05K2203/1536 ,  H01L2924/00

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

Abstract translation: 用于安装半导体芯片的半导体封装板包括具有用于在其中接收半导体芯片的开口的金属基体和层叠在金属基底上的多层布线膜。 将半导体芯片倒装芯片接合到设置在开口内的多层布线膜上的金属焊盘上。 金属基体的表面与容纳在开口中的半导体芯片的顶表面齐平。 所得的半导体器件在不使用加强件的情况下具有较大数量的外部引脚和较小的变形。