公开(公告)号：US4366540A

公开(公告)日：1982-12-28

申请号：US234004

申请日：1981-02-12

申请人： Neil C. Berglund ,  John R. Burchfiel, Jr.

发明人： Neil C. Berglund ,  John R. Burchfiel, Jr.

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F1/04

CPC分类号： G06F9/223 ,  G06F9/267

摘要： A system for controlling the cycle time of a central processing unit having associated control store memory units for the storage of information is provided. The system includes a plurality of control store memory locations disposed within the control store memory units for the storage of information. A plurality of control store memory locations are operable at varying speeds and are accessible by the central processing unit. Circuitry is provided for addressing one of the plurality of control store memory locations responsive to address information contained within the information stored within the plurality of control store memory locations. The addressed information selects the next successive control store memory location to be addressed by a central processing unit. The system further includes logic circuitry for dynamically controlling the cycle time of the central processing unit in response to the addressed information and the speed of the location of the next successive one of the plurality of control store memory locations to be accessed by the central processing unit where the cycle time of the central processing unit automatically adjusts to the speed of the next successive addressed control store memory location.

摘要翻译： 提供一种用于控制具有用于存储信息的相关联的控制存储单元的中央处理单元的周期时间的系统。 该系统包括设置在控制存储器单元内用于存储信息的多个控制存储器存储单元。 多个控制存储器存储器位置以可变速度操作并且可由中央处理单元访问。 电路被提供用于响应于包含在存储在多个控制存储器存储器位置内的信息中的地址信息来寻址多个控制存储存储单元之一。 所寻址的信息选择要由中央处理单元寻址的下一个连续控制存储器存储器位置。 该系统还包括逻辑电路，用于响应于所寻址的信息和中央处理单元要访问的多个控制存储器存储器位置中的下一个连续的一个控制存储器存储单元的位置的速度动态地控制中央处理单元的周期时间 其中中央处理单元的周期时间自动调整到下一个连续寻址控制存储器存储器位置的速度。

公开(公告)号：US4364075A

公开(公告)日：1982-12-14

申请号：US182870

申请日：1980-09-02

申请人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

发明人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

IPC分类号： G11C11/401 ,  G11C5/00 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/556 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/10805 ,  G11C11/404 ,  G11C5/005 ,  H01L23/556 ,  H01L2924/0002

摘要： A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

摘要翻译： 公开了一种包括形成在n阱中的晶体管和电容装置的高密度CMOS动态RAM单元。 电容装置包括设置在形成在n阱中的p型区域上方的多晶硅板构件。 从板构件延伸的埋入触头刺穿p型区域并与阱接触。 除了与板构件，p型区域和阱相关联的电容之外，在n型区域和p型区域的侧壁之间获得电容。

公开(公告)号：US4258417A

公开(公告)日：1981-03-24

申请号：US954067

申请日：1978-10-23

申请人： Neil C. Berglund ,  David A. Luick

发明人： Neil C. Berglund ,  David A. Luick

IPC分类号： G06F13/12 ,  G06F9/22 ,  G06F9/30 ,  G06F12/00 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4243

摘要： Improved efficiency in the operation of a computer system is achieved by interface logic that controls the operating rate of a central processing unit to be compatible with the slower operating rate of main memory. Microinstructions are decoded and interlock latches are generated to provide a main store interface holdoff signal that is applied to holdoff latch logic. Normally, the holdoff latch logic provides load control signals to sequence the operating cycle of the central processing unit. Under certain identified microinstruction conditions, an interlock latch is generated and the load control signals are not output from the holdoff logic, thereby inhibiting the sequencing operation of the central processing unit. Interlock latches that are generated include a register-in-use interlock and an invalid data interlock for each register that is used to fetch data from and store data into main memory.

摘要翻译： 通过控制中央处理单元的运行速率与主存储器的较慢运行速率兼容的接口逻辑来实现计算机系统的运行效率的提高。 对微指令进行解码，产生互锁锁存器，以提供应用于缓存锁存逻辑的主存储接口缓存信号。 通常，释放锁存逻辑提供负载控制信号以对中央处理单元的操作周期进行排序。 在某些确定的微指令条件下，产生互锁锁存器，并且负载控制信号不从释放逻辑输出，从而阻止中央处理单元的排序操作。 生成的互锁锁存器包括用于从每个寄存器中使用的寄存器使用互锁和无效数据互锁，用于从数据库中获取数据并将数据存储到主存储器中。

公开(公告)号：US5646509A

公开(公告)日：1997-07-08

申请号：US565873

申请日：1995-12-01

申请人： Neil C. Berglund ,  Todd J. Rosedahl ,  Steven W. Steele

发明人： Neil C. Berglund ,  Todd J. Rosedahl ,  Steven W. Steele

IPC分类号： G01R31/36 ,  H02J7/00 ,  H01M10/44 ,  G01N27/416 ,  H02J9/04

CPC分类号： G01R19/16542 ,  G01R31/3648 ,  H02J7/0022 ,  Y10S320/21 ,  Y10T307/625

摘要： A battery capacity test and electronic system implementing the same tests both the high and low discharge capacities of a back-up battery to ensure that the battery is capable of handling both a short term, high discharge load and a long term, low discharge load. The battery capacity test is particularly suitable for use in an electronic system which, upon occurrence of a power outage, converts from an operational mode to a power saving mode during a conversion time. High discharge capacity testing is performed using a "safety net" where the primary power source of the electronic system is switched to a reduced testing voltage output, rather than shut off or disconnected, so that the primary power source can take over quickly in the event of a back-up power supply failure during the test.

摘要翻译： 实现相同测试的电池容量测试和电子系统测试备用电池的高放电容量和低放电容量，以确保电池能够处理短期，高放电负载和长期低放电负载。 电池容量测试特别适用于在发生停电时在转换时间内从操作模式转换为省电模式的电子系统。 使用“安全网”进行高放电容量测试，其中电子系统的主电源被切换到降低的测试电压输出，而不是切断或断开，从而主电源可以在事件中快速接管 在测试期间备用电源故障。

公开(公告)号：US4298927A

公开(公告)日：1981-11-03

申请号：US954068

申请日：1978-10-23

申请人： Neil C. Berglund ,  William G. Kempke ,  William C. Richardson

发明人： Neil C. Berglund ,  William G. Kempke ,  William C. Richardson

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/3802

摘要： A digital computer system including a computation unit (14), a main store (12), a virtual address translator (10), a microinstruction control unit (170) and an instruction code prefetch circuit (212). User instruction codes are stored sequentially in the main store (12) which is accessed for read and write operations by the virtual address translator (10). The instruction code prefetch circuit (212) retrieves the user instruction codes from the main store (12) and holds the instruction codes in a register (16, 18). The instruction codes are transferred from the register (16, 18) to the computation unit (14) in sequential order of use. The microinstruction control unit (170) produces selected microinstructions which are executed by the computation unit (14) to accomplish the operations specified by the user instructions. Designated microinstructions include commands which activate the instruction code prefetch circuit (212) to retrieve the succeeding user instruction codes from the main store (12).

摘要翻译： 一种数字计算机系统，包括计算单元（14），主存储器（12），虚拟地址转换器（10），微指令控制单元（170）和指令代码预取电路（212）。 用户指令码顺序存储在由虚拟地址转换器（10）读取和写入操作的主存储器（12）中。 指令代码预取电路（212）从主存储器（12）检索用户指令代码，并将指令代码保存在寄存器（16,18）中。 指令码按照使用顺序从寄存器（16,18）传送到计算单元（14）。 微指令控制单元（170）产生由计算单元（14）执行以完成由用户指令指定的操作的所选微指令。 指定的微指令包括激活指令代码预取电路（212）以从主存储器（12）检索后续用户指令代码的命令。

公开(公告)号：US4268902A

公开(公告)日：1981-05-19

申请号：US953673

申请日：1978-10-23

申请人： Neil C. Berglund ,  James R. Nieling

发明人： Neil C. Berglund ,  James R. Nieling

IPC分类号： G06F13/00 ,  G06F9/00 ,  G06F11/273 ,  G06F11/00

CPC分类号： G06F11/2733

摘要： A maintenance interface is provided for interfacing a service processor and a central processing unit operating asynchronously to each other. The maintenance interface includes circuitry for synchronizing the service processor to the central processing unit and decode circuitry for interpreting commands from the service processor. The maintenance interface also includes circuitry responsive to control signals from the central processing unit such that the maintenance interface establishes communication between the service processor and the central processing unit. The central processing unit includes a microprocessor for interpreting data sent between the service processor and the central processing unit. The maintenance interface is responsive to control signals from the central processing unit to resolve communication contention between the central processing unit and the service processor. The maintenance interface further facilitates the use of the LSSD testing procedure by degating central processing unit interfaces as required for this testing approach.

摘要翻译： 提供了维护接口，用于将服务处理器与彼此异步操作的中央处理单元进行接口。 维护接口包括用于将服务处理器同步到中央处理单元的电路和用于解释来自服务处理器的命令的解码电路。 维护接口还包括响应于来自中央处理单元的控制信号的电路，使得维护接口在服务处理器和中央处理单元之间建立通信。 中央处理单元包括用于解释在服务处理器和中央处理单元之间发送的数据的微处理器。 维护接口响应于来自中央处理单元的控制信号，以解决中央处理单元和服务处理器之间的通信争用。 维护界面进一步有助于通过按照本测试方法的要求对中央处理单元接口进行去光处理来使用LSSD测试程序。

公开(公告)号：US4262330A

公开(公告)日：1981-04-14

申请号：US954069

申请日：1978-10-23

申请人： Neil C. Berglund ,  Richard D. Crowley ,  William G. Kempke ,  William C. Richardson

发明人： Neil C. Berglund ,  Richard D. Crowley ,  William G. Kempke ,  William C. Richardson

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/06

CPC分类号： G06F9/3017 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/30181

摘要： A control system for a computer includes a control store (30) for storing end op, I-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next microinstruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to I-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to I-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (3) to being E-phase.

摘要翻译： 一种用于计算机的控制系统包括用于存储结束操作，I-1，I-2和返回字的控制存储器（30）。 微指令解码和控制单元（170）响应终端op词来初始化和个性化计算机组件以便于后续执行高级指令。 控制单元（170）结合下一个地址逻辑（162），响应于高电平指令选择要执行的下一个微指令。 控制单元（170）和逻辑（162）响应I-1个字来个性化计算机并选择微指令以开始高电平指令的E相。 响应于I-2控制字，控制单元（170）和逻辑（162）在控制存储器（30）中选择操作数获取程序，并将第一E相地址写入本地存储器（138）。 返回字从本地存储器（138）门控第一个E相地址，以选择控制存储器（3）中的微指令为E相。

公开(公告)号：US06181029B2

公开(公告)日：2001-01-30

申请号：US09187067

申请日：1998-11-06

申请人： Neil C. Berglund ,  Patrick K. Egan ,  Steven W. Steele ,  John V. Swenson

发明人： Neil C. Berglund ,  Patrick K. Egan ,  Steven W. Steele ,  John V. Swenson

IPC分类号： H02J900

CPC分类号： H02M1/4225 ,  H02J9/062 ,  H02M2001/007 ,  H02M2001/008 ,  Y02B70/126 ,  Y10T307/625

摘要： A power system includes a battery back-up unit (BBU) having back-up battery circuitry which provides battery back-up support for a plurality of power supplies each having a respective power factor correction circuit front-end with a boost stage. The voltages output from the boost stages of the power supplies are monitored and compared with respective reference threshold voltages to derive a signal which is used to bring battery back-up power on-line when a monitored voltage falls below a threshold voltage, which may be indicative of a loss of AC mains input voltage. AC mains input voltage is also monitored to detect a restoration and disconnect the battery back-up power. In the event that battery back-up is brought on-line due to a faulty power supply rather than a loss of AC mains input voltage, the faulty power supply can be masked and reported for repair.

摘要翻译： 电力系统包括具有备用电池电路的电池备用单元（BBU），其为多个电源提供电池备用支持，每个电源具有带有升压级的相应的功率因数校正电路前端。 从电源的升压级输出的电压被监测并与相应的参考阈值电压进行比较，以导出当监视的电压下降到阈值电压以下时在线使电池备用电源的信号，其可以是 表示交流电源输入电压损失。 还监控交流电源输入电压以检测恢复并断开电池备用电源。 如果由于电源故障而导致电池备份而不是交流电源输入电压的损失而导致电池备份，则故障电源可以被屏蔽并报告进行维修。

公开(公告)号：US5117430A

公开(公告)日：1992-05-26

申请号：US652760

申请日：1991-02-08

申请人： Neil C. Berglund

发明人： Neil C. Berglund

IPC分类号： G06F13/00 ,  H04L12/403

CPC分类号： H04L12/44 ,  H04L12/403 ,  H04L12/4035

摘要： A plurality of nodes in a network are connected in a tree arrangement. A master control node is at the root of the tree. Each connection between a parent node and a child node in the tree consists of only one pair of wires, over which data bits are transmitted serially. To avoid contention, communications are always initiated by the parent node. The child node detects the end of message when no more data is received for a set timeout period. The child node then has a specified time interval for response to the communication, during which interval it has control of the line. After the end of the interval, control reverts to the parent. If a message has been received from the child within that time, normal status is resumed; oterwise, the parent retries the message or takes other error recovery actions. In the preferred embodiment, the network is used to monitor power conditions at a plurality of nodes in a computer system.

公开(公告)号：US4730251A

公开(公告)日：1988-03-08

申请号：US791884

申请日：1985-10-28

申请人： David E. Aakre ,  Douglas J. Abrahamson ,  Neil C. Berglund ,  Vincent A. Bettermann ,  Lloyd S. Heim ,  Kenneth A. Moe

发明人： David E. Aakre ,  Douglas J. Abrahamson ,  Neil C. Berglund ,  Vincent A. Bettermann ,  Lloyd S. Heim ,  Kenneth A. Moe

IPC分类号： G06F13/14 ,  G06F12/06 ,  G06F9/00

CPC分类号： G06F12/0661

摘要： An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit position in the bit string is selected by the host in a serial manner with the host specifying which binary value is being solicited. All devices whose identifier digit matches the solicited value respond positively and remain in contention for address assignment. The other devices will not respond and drop out of contention for address assignment until the sequence is restarted from the first bit. After the bit sequence is completed, the address for that device is bused to the device, and the sequence is restarted from the first bit until all devices have been assigned an address.

摘要翻译： 自动地址分配系统具有耦合到总线的多个I / O设备。 每个设备都包含一个独特的机器可读标识符，用于选择用于地址分配的设备。 标识符是二进制位串。 主机以串行方式选择位串中的每个位位置，主机指定要求哪个二进制值。 标识符数字与被请求值相匹配的所有设备都会积极响应，并保持争用地址分配。 其他设备不会响应并退出地址分配的争用，直到序列从第一个位重新启动。 在比特序列完成后，该设备的地址被引用到设备，并且从第一个位重新启动序列，直到所有设备都被分配了一个地址。