公开(公告)号：US20120199987A1

公开(公告)日：2012-08-09

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08178396B2

公开(公告)日：2012-05-15

申请号：US12402103

申请日：2009-03-11

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L21/82

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08552568B2

公开(公告)日：2013-10-08

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用这种方法形成包括其的新型半导体器件和结构。

公开(公告)号：US20100230724A1

公开(公告)日：2010-09-16

申请号：US12402103

申请日：2009-03-11

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08735902B2

公开(公告)日：2014-05-27

申请号：US12776965

申请日：2010-05-10

申请人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

发明人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC分类号： H01L21/8239

CPC分类号： H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。

公开(公告)号：US08707278B2

公开(公告)日：2014-04-22

申请号：US13251463

申请日：2011-10-03

申请人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

发明人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

IPC分类号： G06F9/45

CPC分类号： G06F8/4434 ,  G06F8/24 ,  G06F8/443 ,  G06F8/51 ,  G06F8/75

摘要： A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

摘要翻译： 提供了一个模型，用于使用由继承引发的先验给定的类层次结构来转换程序。 继承去除器配置为从给定的程序中删除继承，以生成一个不包含与继承相关的操作相关联的虚拟函数指针表和运行时库的分析友好的程序。 分析友好的程序保留给定程序相对于给定类层次结构的语义。 澄清器被配置为识别隐式表达式和函数调用，并将给定程序转换成具有显式表达式和函数调用的至少一个中间程序。

公开(公告)号：US08592254B2

公开(公告)日：2013-11-26

申请号：US13612337

申请日：2012-09-12

申请人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

发明人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

公开(公告)号：US08508997B2

公开(公告)日：2013-08-13

申请号：US12646847

申请日：2009-12-23

申请人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

发明人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

IPC分类号： G11C11/34

CPC分类号： H01L27/11551 ,  G11C16/0458 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.

摘要翻译： 本发明的实施例涉及垂直存储器结构。 本发明的实施例描述了在分离源区和漏区的垂直沟道的相对侧上包括两个存储单元的存储器节点。 本发明的实施例可以利用浮动栅极NAND存储器单元，多晶硅二极管，MiM二极管或者MiiM二极管。 本发明的实施例可用于形成闪速存储器，RRAM，忆阻器RAM，氧化物Ram或OTPROM。

公开(公告)号：US08431184B2

公开(公告)日：2013-04-30

申请号：US13103050

申请日：2011-05-07

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： B05D5/12

CPC分类号： H01L21/76877 ,  C25D5/02 ,  C25D5/04 ,  C25D5/08 ,  C25D5/10 ,  C25D21/10 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879

摘要： Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

摘要翻译： 一些实施例包括在高纵横比开口和低纵横比开口内形成导电材料的方法。 首先，高纵横比开口可以填充第一导电材料，而低纵横比开口仅部分地填充有第一导电材料。 然后可以在高纵横比开口内相对于第一导电材料，在低纵横比开口内的第一导电材料上选择性地镀覆附加材料。 在一些实施例中，附加材料可以是仅部分填充低纵横比开口的活化材料，并且可以随后将另一种导电材料电镀到活化材料上以填充低纵横比开口。

公开(公告)号：US20120187335A1

公开(公告)日：2012-07-26

申请号：US13413157

申请日：2012-03-06

申请人： Nishant Sinha ,  J. Neil Greeley

发明人： Nishant Sinha ,  J. Neil Greeley

IPC分类号： C09K13/08 ,  C09K13/00

CPC分类号： C09K13/08 ,  C09K13/06 ,  H01L21/31055 ,  H01L21/31111

摘要： Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.

摘要翻译： 在膜或其他结构中由接缝，键孔和其它异常形成的角部处的各向同性物质的各向同性除去方法包括使用蚀刻阻挡剂来覆盖或涂覆这些角。 这种覆盖物或涂层防止角部暴露于各向同性蚀刻溶液和清洁溶液，并且因此防止在角部比在结构或膜的平滑区域更高的材料去除速率。 还公开了包括至少一种类型的蚀刻阻挡剂的解决方案，包括湿蚀刻剂和清洁溶液，以及用于防止在膜或其它结构中由接缝，缝隙或凹陷形成的拐角处更高速率的材料去除的系统。 还公开了其中蚀刻阻挡剂被定位以防止各向同性蚀刻剂从不期望的高速率的膜或其它结构的表面中的接缝，裂缝或凹陷的角落移除材料的半导体器件结构。