公开(公告)号：US20120199987A1

公开(公告)日：2012-08-09

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08178396B2

公开(公告)日：2012-05-15

申请号：US12402103

申请日：2009-03-11

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L21/82

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08552568B2

公开(公告)日：2013-10-08

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用这种方法形成包括其的新型半导体器件和结构。

公开(公告)号：US20100230724A1

公开(公告)日：2010-09-16

申请号：US12402103

申请日：2009-03-11

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08969948B2

公开(公告)日：2015-03-03

申请号：US13852988

申请日：2013-03-28

申请人： Fatma A. Simsek-Ege ,  Krishna K. Parat

发明人： Fatma A. Simsek-Ege ,  Krishna K. Parat

IPC分类号： H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/3088 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32134 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4933 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.

摘要翻译： 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 在制造存储器件期间，使用钨硅化物作为蚀刻停止层代替常规使用的氧化铝以形成具有高纵横比的通道柱。 使用钨硅化物可用于消除不期望的蚀刻停止凹部和当通常使用Al氧化物蚀刻停止层时形成的不需要的浮动栅极。

公开(公告)号：US08816489B2

公开(公告)日：2014-08-26

申请号：US13471048

申请日：2012-05-14

申请人： Gurtej S. Sandhu ,  Krishna K. Parat

发明人： Gurtej S. Sandhu ,  Krishna K. Parat

IPC分类号： H01L23/02 ,  H01L21/30

CPC分类号： H01L23/538 ,  H01L21/76254 ,  H01L21/78 ,  H01L21/8221 ,  H01L23/3185 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

摘要翻译： 公开了在没有电路的受主基板上制造集成电路器件的方法。 集成电路器件通过在接受器衬底上依次布置一个或多个半导体材料层并且在配置下一较高电平之前在每个级别的半导体材料上制造电路而形成。 在封装电路之后，去除受主衬底并切割半导体晶片。 还公开了通过这些方法形成的集成电路器件。

公开(公告)号：US20130044549A1

公开(公告)日：2013-02-21

申请号：US13210194

申请日：2011-08-15

申请人： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

发明人： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC分类号： G11C16/04 ,  H01L29/78 ,  H01L29/788

CPC分类号： G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

摘要： Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

摘要翻译： 公开了装置和方法，例如包括与柱（例如半导体材料）相关联的一串电荷存储装置的装置，源极栅极装置和耦合在源栅极装置和串之间的源极选择装置。 描述附加的装置和方法。

公开(公告)号：US20120327713A1

公开(公告)日：2012-12-27

申请号：US13165416

申请日：2011-06-21

申请人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

发明人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

摘要翻译： 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US08945996B2

公开(公告)日：2015-02-03

申请号：US13085083

申请日：2011-04-12

申请人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

发明人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC分类号： H01L23/52 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

摘要翻译： 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US08624300B2

公开(公告)日：2014-01-07

申请号：US12969975

申请日：2010-12-16

申请人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

发明人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

IPC分类号： H01L23/52

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

摘要翻译： 简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。 隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。