Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US06862220B2

    公开(公告)日:2005-03-01

    申请号:US10886725

    申请日:2004-07-09

    摘要: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

    摘要翻译: 包括安装在芯片上的非易失性存储单元和可变逻辑单元的半导体器件被配置为在较低电压下实现更高速度的操作。 半导体器件包括:非易失性存储器单元,其包括多个可重写非易失性存储器单元,以及根据要加载到其存储单元中的逻辑构造定义数据确定其逻辑功能的可变逻辑单元。 非易失性存储单元基本上具有由选择MOS晶体管和存储器MOS晶体管构成的分离栅极结构,并且被构造成使得选择MOS晶体管的栅极的介电耐受电压低于存储器MOS晶体管或栅极绝缘 选择MOS晶体管的层比耐高压MOS晶体管薄。 由于选择MOS晶体管具有高Gm,因此可以获得足够大的读取电流。

    Microprocessor and method for setting up its peripheral functions
    3.
    发明授权
    Microprocessor and method for setting up its peripheral functions 失效
    微处理器和设置其外设功能的方法

    公开(公告)号:US5307464A

    公开(公告)日:1994-04-26

    申请号:US621641

    申请日:1990-12-03

    IPC分类号: G06F13/12 G06F15/78 G06F13/00

    CPC分类号: G06F13/124 G06F15/7814

    摘要: A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.

    摘要翻译: 单片微处理器1包括用于软件实现微处理器1的外围功能的CPU 2和子处理器5.子处理器5包括电可写内部存储设备微程序存储单元13和用于存储软件的顺控控制存储单元62 。 通过将软件写入存储器单元13和62来定义和/或修改外围功能。因此,定义和/或修改外围功能所花费的时间是编程存储器单元13和62所花费的时间。子 处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14.另外,微程序存储单元13向执行单元16提供微指令。顺序控制存储器 单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。 顺序控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11的选择顺序的信息。 每次读序列控制存储器单元62选择地址寄存器MAR0至MAR11中的一个。 存储在选择的地址寄存器中的微地址然后被提供给微程序存储单元13。

    Integrated circuit having processor coupled by common bus to
programmable read only memory for processor operation and processor
uncoupled from common bus when programming read only memory from
external device

    公开(公告)号:US5088023A

    公开(公告)日:1992-02-11

    申请号:US358523

    申请日:1989-05-30

    CPC分类号: G06F15/7842 G06F15/786

    摘要: The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal, wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.

    Microprocessor for carrying out a plurality of different microprograms
at the same time and method for controlling the microprocessor
    6.
    发明授权
    Microprocessor for carrying out a plurality of different microprograms at the same time and method for controlling the microprocessor 失效
    用于同时执行多个不同微程序的微处理器以及用于控制微处理器的方法

    公开(公告)号:US5410658A

    公开(公告)日:1995-04-25

    申请号:US960505

    申请日:1992-10-13

    CPC分类号: G06F9/28 G06F9/3851

    摘要: The inventive microprocessor includes a first section which runs a microprogram pertinent to a macroinstruction and a second section which runs microprograms that are independent of the macroinstruction, with the first and second sections being operated selectively under time-division control. The microprocessor operates by either selecting one of a plurality of microaddress registers or a macroinstruction register, and by reading out the contents of the selected register for use as an address of a microinstruction memory, carrying out a process based on a microinstruction read out of the microinstruction memory in accordance with the address and generating a next macroinstruction address or next microinstruction address, making access to a macroinstruction memory in accordance with the next macroinstruction address thereby to read out a next macroinstruction, loading the next macroinstruction into the macroinstruction register, selecting one of the microaddress registers and loading the next microinstruction address into the selected microinstruction register, and controlling the selecting operations on a time-division basis.

    摘要翻译: 本发明的微处理器包括运行与宏指令相关的微程序的第一部分和运行独立于宏指令的微程序的第二部分,其中第一和第二部分选择性地在时分控制下操作。 微处理器通过选择多个微地址寄存器或宏指令寄存器之一进行操作,并且通过读出所选择的寄存器的内容以用作微指令存储器的地址,执行基于从该指令读出的微指令的处理 微指令存储器根据地址生成下一个宏指令地址或下一个微指令地址,根据下一个宏指令地址访问宏指令存储器,从而读出下一个宏指令,将下一个宏指令加载到宏指令寄存器中,选择一个 的微地址寄存器,并将下一个微指令地址加载到所选择的微指令寄存器中,并且以时分方式控制选择操作。

    Microcomputer having a PROM including data security and test circuitry
    7.
    发明授权
    Microcomputer having a PROM including data security and test circuitry 失效
    具有PROM的微型计算机,包括数据安全和测试电路

    公开(公告)号:US5175840A

    公开(公告)日:1992-12-29

    申请号:US726113

    申请日:1991-06-21

    IPC分类号: G06F12/14

    CPC分类号: G06F12/1433

    摘要: Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate or body. The second inhibition means is coupled to the data bus and provides a second inhibiting operation to prevent access operations to the memory from outside the semiconductor body via the data bus and permanently disables the access operations to the memory irrespective of a releasing or termination of the first inhibiting operation after the second inhibiting operation has taken effect.

    摘要翻译: 电可擦除可编程只读存储器(EEPROM)的易测试性和数据安全性可以通过设置焊盘和输入/输出(I / O)电路来实现,该电路提供半导体衬底上的EEPROM测试所需的地址,数据和控制信号, 通过在基板上布置由EEPROM器件组成的两级测试I / O截取电路,使得一旦完成测试,由于具有内置的数据安全功能,防止了对半导体衬底之外的非法存取。 具有这种能力的微型计算机设置有用于处理数据的中央处理单元(CPU),诸如EEPROM的存储器,其通过公共总线(其传送数据,地址和控制信号)与CPU进行内部通信,其他 比在测试模式期间以及提供安全性的第一和第二抑制电路。 第一禁止电路耦合到数据总线,并提供第一禁止操作以防止对存储器的访问操作。 第一抑制电路根据来自半导体衬底或主体外部的信号来释放第一禁止操作。 第二禁止装置耦合到数据总线,并且提供第二禁止操作,以防止经由数据总线从半导体主体外部对存储器的访问操作,并且永久地禁用对存储器的访问操作,而不管第一 第二禁止操作之后的禁止操作已经起作用。

    Semiconductor logic device having two-dimensional logic arrays and logic
cell chains alternately arranged
    9.
    发明授权
    Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged 失效
    具有交替布置的具有二维逻辑阵列和逻辑单元链的半导体逻辑器件

    公开(公告)号:US4982114A

    公开(公告)日:1991-01-01

    申请号:US343289

    申请日:1989-04-26

    IPC分类号: H01L21/82 H03K19/177

    摘要: A semiconductor logic device having arrays of logic elements and chains of logic cells alternately arranged in a direction substantially perpendicular to the direction of the chains of logic cells in a surface portion of a semiconductor substrate. Each of the logic element arrays has input and output leads extending from the array in the above-mentioned direction substantially perpendicular to the direction of the chains of logic cells so that each of said logic cell chains is in an electrical connection with two adjacent logic element arrays via the input and output leads.

    摘要翻译: 一种半导体逻辑器件,具有在半导体衬底的表面部分中与逻辑单元的链条的方向基本垂直的方向交替布置的逻辑元件和逻辑单元串。 每个逻辑元件阵列具有从阵列沿上述方向延伸的输入和输出引线,该方向基本上垂直于逻辑单元的链条的方向,使得每个逻辑单元链与两个相邻的逻辑元件电连接 阵列通过输入和输出引线。

    Semiconductor integrated circuit with nonvolatile memory
    10.
    发明授权
    Semiconductor integrated circuit with nonvolatile memory 失效
    具有非易失性存储器的半导体集成电路

    公开(公告)号:US4821240A

    公开(公告)日:1989-04-11

    申请号:US174975

    申请日:1988-03-29

    CPC分类号: G11C16/22 G11C7/24

    摘要: A semiconductor integrated circuit with a nonvolatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether operations such as a programming (i.e., writing), erasing or reading with respect to the data memory elements will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element. In other words, data security in an arbitrary area of the matrix can be accomplished based on the content of the protecting data memory element.

    摘要翻译: 具有非易失性存储器的半导体集成电路具有以矩阵形式布置的多个非易失性数据存储器元件和用于根据指定矩阵中的位置的地址信号从存储器元件读取数据的装置。 用于存储至少一位保护数据的保护数据存储元件设置在矩阵中。 根据保护数据存储元件的内容来确定是否允许或禁止关于数据存储器元件的编程(即写入),擦除或读取的操作。 换句话说,可以基于保护数据存储元件的内容来实现矩阵的任意区域中的数据安全性。