公开(公告)号：US20120228743A1

公开(公告)日：2012-09-13

申请号：US13480317

申请日：2012-05-24

申请人： O Seo Park ,  Wai-Kin Li

发明人： O Seo Park ,  Wai-Kin Li

IPC分类号： H01L21/311 ,  H01L21/66 ,  G06F17/50 ,  G03F1/32 ,  G03F1/36 ,  G03F1/26 ,  G03F1/30 ,  H01L29/02 ,  G03B27/68

CPC分类号： H01L21/31144 ,  G03F1/144 ,  G03F1/36 ,  G03F1/80 ,  H01L22/12 ,  H01L22/20

摘要： Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

摘要翻译： 公开了制造半导体器件的方法和光学邻近校正方法的方法。 在一个实施例中，制造半导体器件的方法包括确定用于半导体器件的材料层的RIE工艺的反应离子蚀刻（RIE）滞后量，以及调整用于所述半导体器件的特征的至少一个图案的尺寸 材料层通过调整量来部分补偿确定的RIE滞后量。

公开(公告)号：US08187974B2

公开(公告)日：2012-05-29

申请号：US11960406

申请日：2007-12-19

申请人： O Seo Park ,  Wai-Kin Li

发明人： O Seo Park ,  Wai-Kin Li

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  G03F1/144 ,  G03F1/36 ,  G03F1/80 ,  H01L22/12 ,  H01L22/20

摘要： Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

摘要翻译： 公开了制造半导体器件的方法和光学邻近校正方法的方法。 在一个实施例中，制造半导体器件的方法包括确定用于半导体器件的材料层的RIE工艺的反应离子蚀刻（RIE）滞后量，以及调整用于所述半导体器件的特征的至少一个图案的尺寸 材料层通过调整量来部分补偿确定的RIE滞后量。

公开(公告)号：US07514356B2

公开(公告)日：2009-04-07

申请号：US11069068

申请日：2005-03-01

申请人： Sajan Marokkey ,  O Seo Park ,  Wai-Kin Li ,  Todd C. Bailey

发明人： Sajan Marokkey ,  O Seo Park ,  Wai-Kin Li ,  Todd C. Bailey

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144

摘要： A method of preventing resist line collapse in damascene structures and a structure thereof is disclosed. A damascene pattern for resist lines is enhanced with ribs extending therefrom. The ribs provide mechanical support for resist lines and improve the lithography process for forming the resist lines, particularly when a negative focus is used. The ribs may extend between vias in an underlying material layer. The method results in structurally strong resist lines for damascene structures that are less likely to collapse.

摘要翻译： 公开了一种防止镶嵌结构中的抗蚀层塌陷的方法及其结构。 用于抵抗线的镶嵌图案被从其延伸的肋条增强。 这些肋为抗蚀剂线提供机械支撑，并且改进了用于形成抗蚀剂线的光刻工艺，特别是当使用负焦点时。 肋可以在下面的材料层中的通孔之间延伸。 该方法导致结构上较强的不可能崩溃的镶嵌结构的抗蚀剂线。

公开(公告)号：US08877650B2

公开(公告)日：2014-11-04

申请号：US13480317

申请日：2012-05-24

申请人： O Seo Park ,  Wai-Kin Li

发明人： O Seo Park ,  Wai-Kin Li

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/66 ,  G03F1/36 ,  G03F1/00

CPC分类号： H01L21/31144 ,  G03F1/144 ,  G03F1/36 ,  G03F1/80 ,  H01L22/12 ,  H01L22/20

摘要： Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

摘要翻译： 公开了制造半导体器件的方法和光学邻近校正方法的方法。 在一个实施例中，制造半导体器件的方法包括确定用于半导体器件的材料层的RIE工艺的反应离子蚀刻（RIE）滞后量，以及调整用于所述半导体器件的特征的至少一个图案的尺寸 材料层通过调整量来部分补偿确定的RIE滞后量。

公开(公告)号：US20090160027A1

公开(公告)日：2009-06-25

申请号：US11960406

申请日：2007-12-19

申请人： O Seo Park ,  Wai-Kin Li

发明人： O Seo Park ,  Wai-Kin Li

IPC分类号： H01L21/66 ,  H01L29/06 ,  G06F17/50

CPC分类号： H01L21/31144 ,  G03F1/144 ,  G03F1/36 ,  G03F1/80 ,  H01L22/12 ,  H01L22/20

摘要： Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

摘要翻译： 公开了制造半导体器件的方法和光学邻近校正方法的方法。 在一个实施例中，制造半导体器件的方法包括确定用于半导体器件的材料层的RIE工艺的反应离子蚀刻（RIE）滞后量，以及调整用于所述半导体器件的特征的至少一个图案的尺寸 材料层通过调整量来部分补偿确定的RIE滞后量。

公开(公告)号：US09046788B2

公开(公告)日：2015-06-02

申请号：US12122929

申请日：2008-05-19

申请人： Allen H. Gabor ,  Wai-Kin Li

发明人： Allen H. Gabor ,  Wai-Kin Li

IPC分类号： G03B27/52 ,  G03B27/68 ,  G03F7/20

CPC分类号： G03F7/70333 ,  G03F7/70508 ,  G03F7/70641

摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

摘要翻译： 提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。 本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。 基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。 在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。 可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

公开(公告)号：US08513769B2

公开(公告)日：2013-08-20

申请号：US12765275

申请日：2010-04-22

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/5256 ,  H01L23/5329 ,  H01L21/7682

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US08398868B2

公开(公告)日：2013-03-19

申请号：US12468391

申请日：2009-05-19

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

IPC分类号： B44C1/22 ,  H01L21/302 ,  H01L21/312

CPC分类号： B81C1/00031 ,  B81C1/00404 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/31144

摘要： An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

摘要翻译： 例如使用光刻法形成衬底中的开口，其中开口具有侧壁，其横截面由轮廓和凸形的部分给出。 例如，开口的横截面可以由重叠的圆形区域给出。 侧壁在各个点处相邻，在那里它们限定突起。 将包含嵌段共聚物的聚合物层施加在开口和基底上，并允许自组装。 在开口中形成离散的，分离的畴，其被去除以形成孔，其可以转移到下面的基底中。 这些区域及其对应的孔的位置通过侧壁及其相关联的突起被引导到预定位置。 分离这些孔的距离可以大于或小于如果嵌段共聚物（和任何添加剂）在没有任何侧壁的情况下自组装就会发生。

公开(公告)号：US08395228B2

公开(公告)日：2013-03-12

申请号：US12941375

申请日：2010-11-08

申请人： Wai-Kin Li ,  Wu-Song Huang ,  Dario Leonardo Goldfarb ,  Martin Glodde ,  Edward Engbrecht ,  Yiheng Xu

发明人： Wai-Kin Li ,  Wu-Song Huang ,  Dario Leonardo Goldfarb ,  Martin Glodde ,  Edward Engbrecht ,  Yiheng Xu

IPC分类号： H01L21/02

CPC分类号： H01L21/0332 ,  G03F7/091 ,  G03F7/094 ,  G03F9/7026

摘要： A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.

摘要翻译： 描述了改善半导体晶片的聚焦调平响应的方法。 该方法包括在半导体衬底上组合有机和无机或金属近红外（NIR）硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层（ARC）层; 以及在所述ARC层上形成光致抗蚀剂层。 还描述了半导体结构，其包括基板，位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。 吸收层包括无机或金属NIR吸收硬掩模层。

公开(公告)号：US08227307B2

公开(公告)日：2012-07-24

申请号：US12490353

申请日：2009-06-24

申请人： Kuang-Jung Chen ,  Ricardo A. Donaton ,  Wu-Song Huang ,  Wai-Kin Li

发明人： Kuang-Jung Chen ,  Ricardo A. Donaton ,  Wu-Song Huang ,  Wai-Kin Li

IPC分类号： H01L21/8238 ,  H01L21/31

CPC分类号： H01L21/31122 ,  H01L21/823842 ,  H01L21/823857

摘要： The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

摘要翻译： 本发明提供一种形成阈值电压调节的栅极叠层的方法，其中使用外部酸扩散工艺来从半导体衬底的一个器件区域选择性地去除一部分阈值电压调节层。 外部酸扩散方法使用酸性聚合物，其在烘烤时表现出酸浓度的增加，其可以扩散到阈值电压调节层的下部暴露部分。 扩散的酸与阈值电压调节层的暴露部分反应，提供酸反应层，与不暴露于扩散的酸的阈值电压调节层的横向相邻部分相比，可以选择性地除去酸反应层。