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    METHOD FOR IMPROVED DIELECTRIC PERFORMANCE
    2.
    发明申请
    METHOD FOR IMPROVED DIELECTRIC PERFORMANCE 审中-公开
    改进电介质性能的方法

    公开(公告)号：US20080044986A1

    公开(公告)日：2008-02-21

    申请号：US11465575

    申请日：2006-08-18

    申请人： Olaf Storbeck ,  Wieland Pethe

    发明人： Olaf Storbeck ,  Wieland Pethe

    IPC分类号： H01L21/477

    CPC分类号： H01L21/28176 ,  H01L21/28185 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/517

    摘要： A method of decreasing the density of dielectric interface traps in an integrated circuit device. In accordance with the teachings of the present invention, the method includes providing a semiconductor substrate, processing the semiconductor substrate to form an integrated circuit device, such as a field effect transistor including forming a dielectric layer, and heating the dielectric layer in an atmosphere comprising at least one gaseous halogen compound.

    摘要翻译： 一种降低集成电路器件中介质界面阱的密度的方法。 根据本发明的教导，所述方法包括提供半导体衬底，处理半导体衬底以形成集成电路器件，例如包括形成电介质层的场效应晶体管，以及在包括 至少一种气态卤素化合物。

    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    4.
    发明申请
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US20050118777A1

    公开(公告)日：2005-06-02

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/31 ,  H01L21/314 ,  H01L21/318 ,  H01L21/334 ,  H01L21/469 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。

    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    7.
    发明授权
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US07547646B2

    公开(公告)日：2009-06-16

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。