公开(公告)号：US10439034B2

公开(公告)日：2019-10-08

申请号：US16188332

申请日：2018-11-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takashi Hasegawa ,  Kouichi Saitou ,  Chiaki Kudou

IPC: H01L29/45 ,  H01L23/535 ,  H01L29/40 ,  H01L21/311 ,  H01L21/324 ,  H01L21/768

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.

公开(公告)号：US10439027B2

公开(公告)日：2019-10-08

申请号：US16048488

申请日：2018-07-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chiaki Kudou

IPC: H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/28 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L23/532 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/04

Abstract: Provided is a silicon carbide semiconductor device that is further reduced in resistance. Silicon carbide semiconductor device includes silicon carbide semiconductor layer disposed on a first main surface of substrate, electrode layer containing polysilicon disposed on the silicon carbide semiconductor layer with first insulating layer interposed between the electrode layer and the silicon carbide semiconductor layer, second insulating layer that covers the silicon carbide semiconductor layer and the electrode layer, first silicide electrode that is located in first opening part formed in the first insulating layer and the second insulating layer and forms ohmic contact with a part of the silicon carbide semiconductor layer, and second silicide electrode that is located in second opening part formed in the second insulating layer and is in contact with a part of the electrode layer.

公开(公告)号：US10978367B2

公开(公告)日：2021-04-13

申请号：US16112116

申请日：2018-08-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chiaki Kudou ,  Takashi Hasegawa ,  Kouichi Saitou

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L29/16 ,  H01L21/311 ,  H01L29/872 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.

公开(公告)号：US09543427B2

公开(公告)日：2017-01-10

申请号：US14820555

申请日：2015-08-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chiaki Kudou ,  Haruyuki Sorada ,  Tsuneichiro Sano

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/7802 ,  H01L21/02131 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/32134 ,  H01L21/32137 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

Abstract translation: 半导体器件包括：具有第一导电类型的杂质区的半导体层; 栅极绝缘层，栅绝缘层的至少一部分位于半导体层上; 位于所述栅极绝缘层上并且具有与所述栅极绝缘膜的所述部分接触的第一表面和与所述第一表面相对的第二表面的栅电极; 覆盖栅电极的层间绝缘层; 和与杂质区接触的电极。 栅电极在垂直于半导体层的表面的栅电极的截面中具有与第二表面接触的角部的凹部。 由栅电极和层间绝缘层包围的空腔位于包括凹部的至少一部分的区域中。

公开(公告)号：US09318600B2

公开(公告)日：2016-04-19

申请号：US14408052

申请日：2014-01-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chiaki Kudou

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/12 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02529 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/78

Abstract: This silicon carbide semiconductor device includes: a substrate with a principal surface; a silicon carbide layer which is arranged on a side of the principal surface of the substrate and which includes a first impurity region of a first conductivity type; a trench which is arranged in the silicon carbide layer and which has a bottom located in the first impurity region; a trench bottom impurity layer which is arranged in the trench to contact with at least a portion of the bottom of the trench and which is a silicon carbide epitaxial layer of a second conductivity type; a gate insulating film which covers a side surface of the trench and the trench bottom impurity layer; and a gate electrode which is arranged over at least a portion of the gate insulating film that is located inside the trench.

Abstract translation: 该碳化硅半导体器件包括：具有主表面的衬底; 碳化硅层，其布置在所述基板的所述主表面的一侧，并且包括第一导电类型的第一杂质区; 沟槽，其布置在所述碳化硅层中，并且具有位于所述第一杂质区域中的底部; 沟槽底部杂质层，其布置在沟槽中以与沟槽的底部的至少一部分接触，并且是第二导电类型的碳化硅外延层; 覆盖所述沟槽的侧面和所述沟槽底部杂质层的栅极绝缘膜; 以及设置在位于沟槽内的栅极绝缘膜的至少一部分上的栅电极。

公开(公告)号：US09269765B2

公开(公告)日：2016-02-23

申请号：US14510125

申请日：2014-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chiaki Kudou

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/16 ,  H01L29/51 ,  H01L29/49 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L29/0611 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32139 ,  H01L23/4824 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.

Abstract translation: 本公开的半导体器件包括设置在基板的主表面上的半导体层。 电池区域设置有设置在半导体层上的栅极绝缘膜和设置在栅极绝缘膜上的栅电极，并且布线区域设置有设置在半导体层上的场绝缘膜和设置在该场上的栅极线 绝缘膜。 场绝缘膜的端部在与基板的主表面垂直的截面中具有凸形状，并且场绝缘膜的上表面比栅极线的下部的上表面更粗糙， 绝缘膜不配置。