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    METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES
    7.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES 有权
    用自对准接触形成半导体器件的方法和结果器件

    公开(公告)号：US20140070285A1

    公开(公告)日：2014-03-13

    申请号：US13611652

    申请日：2012-09-12

    申请人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

    发明人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

    IPC分类号： H01L21/28 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

    摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

    摘要翻译： 一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层 牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。 该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层， 暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

    Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
    8.
    发明授权
    Methods of forming semiconductor devices with self-aligned contacts and the resulting devices 有权
    形成具有自对准触头的半导体器件的方法以及所产生的器件

    公开(公告)号：US08753970B2

    公开(公告)日：2014-06-17

    申请号：US13611652

    申请日：2012-09-12

    申请人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

    发明人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

    摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

    摘要翻译： 一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层 牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。 该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层， 暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

    MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING
    10.
    发明申请
    MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING 审中-公开
    多层结构的多层掩模方法

    公开(公告)号：US20080305437A1

    公开(公告)日：2008-12-11

    申请号：US11760992

    申请日：2007-06-11

    申请人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

    发明人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

    IPC分类号： G03C5/00

    CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/7833

    摘要： A method for forming a patterned structure within a microelectronic structure uses a non-directly imageable organic material layer located over a substrate and a directly imageable inorganic material layer located upon the non-directly imageable organic material layer. The directly imageable inorganic material layer is directly imaged to form a patterned inorganic material layer. The patterned inorganic material layer is used as a first etch mask within a first etch method that etches the non-directly imageable organic material layer to form a patterned organic material layer. At least the patterned organic material layer is used as a second etch mask within a second etch method that etches the substrate to form a patterned structure within the substrate.

    摘要翻译： 用于在微电子结构内形成图案化结构的方法使用位于基底上的非直接成像的有机材料层和位于不可直接成像的有机材料层上的可直接成像的无机材料层。 可直接成像无机材料层直接成像以形成图案化的无机材料层。 图案化的无机材料层在第一蚀刻方法中用作第一蚀刻掩模，其蚀刻非直接成像的有机材料层以形成图案化的有机材料层。 至少图案化的有机材料层在第二蚀刻方法中用作第二蚀刻掩模，其蚀刻衬底以在衬底内形成图案化结构。