公开(公告)号：US20050106845A1

公开(公告)日：2005-05-19

申请号：US11014464

申请日：2004-12-16

申请人： Patrick Halahan ,  Oleg Siniaguine

发明人： Patrick Halahan ,  Oleg Siniaguine

IPC分类号： H01L29/872 ,  H01L21/3205 ,  H01L21/329 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/552 ,  H01L27/04 ,  H01L29/47 ,  H01L29/861 ,  H01L21/76 ,  H01L21/28 ,  H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/78

CPC分类号： H01L23/552 ,  H01L21/76898 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/3025 ,  Y10S438/977 ,  H01L2924/00

摘要： In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.

摘要翻译： 在一些实施例中，电路结构包括半导体衬底，在衬底的第一侧和衬底的第二侧之间穿过衬底的开口以及开口中的多个导电层。 在一些实施例中，一个导电层提供电磁屏蔽，其屏蔽基板与由衬底背面上的另一导电层制成的接触焊盘承载的交流信号。 导电层也可用于形成电容器/整流器网络。 还提供了制造方法。

公开(公告)号：US06448153B2

公开(公告)日：2002-09-10

申请号：US09752802

申请日：2000-12-28

申请人： Oleg Siniaguine ,  Patrick Halahan ,  Sergey Savastiouk

发明人： Oleg Siniaguine ,  Patrick Halahan ,  Sergey Savastiouk

IPC分类号： H01L21301

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/482 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/14

摘要： A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then, the wafer is placed into a non-contact wafer holder, and the wafer backside is blanket etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and coners. As a result, the chip becomes more reliable, and in particular more resistant to thermal and other stresses.

摘要翻译： 在变薄之前切割半导体晶片。 晶片仅被部分通过切割，以形成至少与从晶片获得的每个芯片的最终厚度相同的凹槽。 然后，将晶片放置在非接触晶片保持器中，并且用干蚀刻（例如，大气压等离子体蚀刻）对晶片背面进行全面蚀刻。 将晶片减薄直到凹槽从背面露出。 干蚀刻使芯片的背面光滑。 在凹槽已经暴露之后，继续进行干法蚀刻以去除芯片侧壁的破坏并绕过芯片的底部边缘和锥体。 结果，芯片变得更可靠，特别是更耐热和其它应力。

公开(公告)号：US20070128868A1

公开(公告)日：2007-06-07

申请号：US11548053

申请日：2006-10-10

申请人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

摘要翻译： 在包括半导体衬底（110）的晶片（104）中形成通孔（114）。 种子层（610）溅射在晶片的底表面上。 种子不会沉积在邻近晶片顶表面的通孔的侧壁上。 导体（810）电镀到通孔中。 在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。 干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。 在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。 通过化学镀在底部形成种子（610）。 导体（810）电镀在种子上。 在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。 非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。 用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。 通过化学镀在底部形成种子（610）。 非保形层可以通过电镀形成。 可以通过电镀沉积钽，然后阳极氧化。 还提供了其他实施例。

公开(公告)号：US20050170647A1

公开(公告)日：2005-08-04

申请号：US11055940

申请日：2005-02-10

申请人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

公开(公告)号：US06749764B1

公开(公告)日：2004-06-15

申请号：US09713137

申请日：2000-11-14

申请人： Oleg Siniaguine ,  Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Oleg Siniaguine ,  Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： B05C300

CPC分类号： H01J37/32761 ,  H01L21/6838

摘要： An article which is being processed with plasma is moved during plasma processing so that the motion of the article comprises at least a first rotational motion, a second rotational motion, and a third rotational motion which occur simultaneously. The apparatus that moves the article comprises a first arm rotatable around a first axis, a second arm rotatably attached to the first arm and rotating the article around a second axis, and a rotational mechanism for inducing a rotational motion of the article in addition to, and simultaneously with, the rotation of the first and second arms.

摘要翻译： 正在等离子体处理的制品在等离子体处理期间移动，使得制品的运动包括同时发生的至少第一旋转运动，第二旋转运动和第三旋转运动。 移动物品的装置包括可围绕第一轴线旋转的第一臂，可旋转地附接到第一臂并使制品围绕第二轴线旋转的第二臂，以及用于引起物品的旋转运动的旋转机构， 并且同时具有第一和第二臂的旋转。

公开(公告)号：US6121571A

公开(公告)日：2000-09-19

申请号：US465989

申请日：1999-12-16

申请人： Oleg Siniaguine ,  Patrick Halahan

发明人： Oleg Siniaguine ,  Patrick Halahan

IPC分类号： H05H1/34 ,  H05H1/36 ,  H05H1/44 ,  B23K9/00

CPC分类号： H05H1/44 ,  H05H1/36 ,  H05H2001/3426 ,  H05H2001/3452

摘要： The present invention relates to ignition circuitry for a plasma generator. A discharge is created by application of a high frequency or high voltage dc ignition pulse between an electrode and a first nozzle. Following ignition, the discharge is redirected to a second nozzle for the purpose of moving the plasma flow from the ignition zone into the zone of application to the workpiece. The present invention is directed to plasma ignition circuitry for improving this performance. Positive thermal coefficient ("PTC") resistance is shown to be useful in reliably and reproducibly switching the arc. Alternative embodiments of the present invention relate to switching the plasma from a first nozzle to a second nozzle then sequentially to additional nozzles downstream in the flow of plasma gas in which PTC resistance is used to reliably and reproducibly effect the switching. Yet other embodiments of the present invention relate to the generation of two plasma jets directed so as to intersect, and switching current flow from the plasma-igniting nozzle electrodes to a direct flow of current from one electrode through the two plasma jets to the second electrode.

摘要翻译： 本发明涉及等离子体发生器的点火电路。 通过在电极和第一喷嘴之间施加高频或高压直流点火脉冲来产生放电。 点火之后，将排放物重定向到第二喷嘴，以将等离子体流从点火区移动到施加到工件的区域中。 本发明涉及用于改善该性能的等离子体点火电路。 正热传导系数（“PTC”）电阻显示可靠，可重复地切换电弧。 本发明的替代实施例涉及将等离子体从第一喷嘴切换到第二喷嘴，然后依次连接到等离子体气体流中的附加喷嘴，其中PTC电阻用于可靠地且可重复地影响切换。 本发明的其它实施例涉及两个等离子体射流的产生，这两个等离子体射流被引导为相交，并且切换来自等离子体点燃喷嘴电极的电流流向从一个电极通过两个等离子体射流到第二电极的直流电流 。

公开(公告)号：US20050212127A1

公开(公告)日：2005-09-29

申请号：US11136799

申请日：2005-05-24

申请人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L29/40 ,  H01L23/52

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

公开(公告)号：US20060035416A1

公开(公告)日：2006-02-16

申请号：US11253943

申请日：2005-10-19

申请人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L21/50 ,  H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

公开(公告)号：US20050133930A1

公开(公告)日：2005-06-23

申请号：US10739707

申请日：2003-12-17

申请人： Sergey Savastisuk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastisuk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/34 ,  H01L23/02

CPC分类号： H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The dies (124) are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.

公开(公告)号：US20050189636A1

公开(公告)日：2005-09-01

申请号：US11123532

申请日：2005-05-05

申请人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/34 ,  H01L23/02

CPC分类号： H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The dies (124) are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.

摘要翻译： 包装衬底（310）包括半导体插入件（120）和至少一个其它中间衬底（110） BT基板。 半导体插入器具有可连接到插入件上方的管芯（124）的第一接触焊盘（136C）和可连接到插入件下方的电路的第二接触焊盘（340）。 在中介层（120）的半导体衬底（140）中形成通孔（330）。 穿过通孔的导电路径将第一接触焊盘（136C）连接到第二接触焊盘（340）。 在将插入件附接到BT基板之后，将管芯（124）附接到插入件。 在顺序焊接操作中，通过在焊接期间将一些材料（例如铜）溶解在焊料中来维持焊料层次，以提高焊料的熔融温度。 例如，所有的焊料最初都可以具有相同的熔化温度，但是在焊接期间每个焊料的熔化温度都会增加，以防止焊料在随后的焊接操作中熔化。