利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.015 秒)

    APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED CIRCUIT
    3.
    发明申请
    APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED CIRCUIT 审中-公开
    在集成电路中组合引脚功能的装置和方法

    公开(公告)号：US20130082764A1

    公开(公告)日：2013-04-04

    申请号：US13250677

    申请日：2011-09-30

    申请人： Paul Penzes ,  Love Kothari ,  Ajat Hukkoo ,  Mark Fullerton ,  Veronica Alarcon ,  Zhongmin Zhang ,  Kerry Alan Thompson ,  Russell Radke

    发明人： Paul Penzes ,  Love Kothari ,  Ajat Hukkoo ,  Mark Fullerton ,  Veronica Alarcon ,  Zhongmin Zhang ,  Kerry Alan Thompson ,  Russell Radke

    IPC分类号： G05F3/02 ,  H03B1/00 ,  G11C5/14

    CPC分类号： G11C29/56 ,  G11C2029/5602

    摘要： An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.

    摘要翻译： 公开了一种在集成电路中组合焊盘功能的装置和方法。 电源，接地或信号焊盘分别连接到电源，接地或信号源。 电源，接地或信号焊盘另外连接到附加信号源，例如测试环境中的自动测试设备。 通过将电源，接地或信号源暂时断开与源传输到的集成电路内的功能块，同一焊盘可以将另一个信号传递到集成电路的其他部分。 在替代方案中，相同的焊盘可以将另一个信号传递到集成电路的其它部分，而不会通过在原始信号上耦合附加信号来断开原始信号。 此外，组合焊盘功能使得可以将输入焊盘重新用作来自集成电路内的信号作为输出焊盘。

    Adaptive ultra-low voltage memory
    4.
    发明授权
    Adaptive ultra-low voltage memory 有权
    自适应超低电压存储器

    公开(公告)号：US08700972B2

    公开(公告)日：2014-04-15

    申请号：US13289691

    申请日：2011-11-04

    申请人： Paul Penzes ,  Mark Fullerton ,  Ajat Hukkoo ,  John Walley

    发明人： Paul Penzes ,  Mark Fullerton ,  Ajat Hukkoo ,  John Walley

    IPC分类号： H03M13/00 ,  G11C29/00

    CPC分类号： G06F1/3275 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/1064 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  H03M13/19 ,  H03M13/3715 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

    摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

    摘要翻译： 实施例提供允许低电压操作模式的自适应存储器。 在低电压工作模式下，提供给存储器的电源电压降至低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗 ）。 根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

    Integrated circuit with pre-heating for reduced subthreshold leakage
    5.
    发明授权
    Integrated circuit with pre-heating for reduced subthreshold leakage 有权
    具有预热功能的集成电路可降低亚阈值泄漏

    公开(公告)号：US08575993B2

    公开(公告)日：2013-11-05

    申请号：US13247694

    申请日：2011-09-28

    申请人： Paul Penzes ,  Mark Fullerton

    发明人： Paul Penzes ,  Mark Fullerton

    IPC分类号： H01L35/00

    CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

    摘要： Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.

    摘要翻译： 某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。 可以看出，在这些半导体工艺中的某些中，高阈值晶体管可以运行的速度随着温度的降低而降低。 因此，实现高阈值晶体管的IC的总体处理速度通常受IC设计（或保证）以适当地起作用的最低温度的限制。 通过“预热”IC（或实现高阈值晶体管的IC的至少部分）来克服这种缺陷的系统和方法的实施例，使得IC可以以高于 在设计（或保证）设计IC（或保证）的给定最低温度下，将提供适当的功能。

    Efficient non-integral multi-height standard cell placement
    7.
    发明授权
    Efficient non-integral multi-height standard cell placement 有权
    高效非积分多高度标准电池放置

    公开(公告)号：US09007095B2

    公开(公告)日：2015-04-14

    申请号：US13467275

    申请日：2012-05-09

    申请人： Paul Penzes

    发明人： Paul Penzes

    IPC分类号： H01L25/00 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

    CPC分类号： G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/00 ,  H01L2924/0002

    摘要： An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

    摘要翻译： 一种集成电路，包括第一单元库的第一部分，所述第一单元库包括第一多行，所述第一多行中的每一行具有第一行高度，所述第一部分具有第一部分高度，所述第二单元库的第二部分包括 第二多行，第二多行中的每一行具有第二行高度，第二部分具有第二部分高度，其中第一部分高度等于第二部分高度，并且第一行高度不同于第二部分高度 行高度以及将第一单元库的第一部分电连接到第二单元库的第二部分的连接器。

    Efficient Non-Integral Multi-Height Standard Cell Placement
    8.
    发明申请
    Efficient Non-Integral Multi-Height Standard Cell Placement 有权
    高效的非积分多高标准细胞放置

    公开(公告)号：US20130214433A1

    公开(公告)日：2013-08-22

    申请号：US13467275

    申请日：2012-05-09

    申请人： Paul Penzes

    发明人： Paul Penzes

    IPC分类号： H01L23/48

    CPC分类号： G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/00 ,  H01L2924/0002

    摘要： An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

    摘要翻译： 一种集成电路，包括第一单元库的第一部分，所述第一单元库包括第一多行，所述第一多行中的每一行具有第一行高度，所述第一部分具有第一部分高度，所述第二单元库的第二部分包括 第二多行，第二多行中的每一行具有第二行高度，第二部分具有第二部分高度，其中第一部分高度等于第二部分高度，并且第一行高度不同于第二部分高度 行高度以及将第一单元库的第一部分电连接到第二单元库的第二部分的连接器。

    High-Speed Standard Cells Designed Using a Deep-Submicron Physical Effect
    9.
    发明申请
    High-Speed Standard Cells Designed Using a Deep-Submicron Physical Effect 有权
    使用深亚微米物理效应设计的高速标准单元

    公开(公告)号：US20110156749A1

    公开(公告)日：2011-06-30

    申请号：US12651109

    申请日：2009-12-31

    申请人： Paul Penzes

    发明人： Paul Penzes

    IPC分类号： H03K19/003 ,  H03K19/00

    CPC分类号： G06F17/5068 ,  G06F17/505 ,  H01L27/0207 ,  H01L27/11807

    摘要： A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.

    摘要翻译： 系统包括信号路径。 有n个信号路径，n是正整数。 第一至第n信号路径中的关键因素是基于具有最慢信号传播的第一至第n信号路径中的相应一个信号传播和/或信号传播速度慢于时钟周期的路径。 第一到第n个信号路径中的关键一个包括包括对应的逻辑设备的标准小区的第一大小。 第一至第n信号路径中的非关键信号包括包括对应的逻辑设备的标准单元的第二大小，第二大小小于第一大小。

    SYSTEMS AND TECHNIQUES FOR DEVELOPING HIGH-SPEED STANDARD CELL LIBRARIES
    10.
    发明申请
    SYSTEMS AND TECHNIQUES FOR DEVELOPING HIGH-SPEED STANDARD CELL LIBRARIES 失效
    用于开发高速标准单元库的系统和技术

    公开(公告)号：US20090083691A1

    公开(公告)日：2009-03-26

    申请号：US11941286

    申请日：2007-11-16

    申请人： Paul Penzes

    发明人： Paul Penzes

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for providing a high-speed cell library is provided. The method can include, for example, selecting a set of commonly-occurring logic functions. The method can then include obtaining a netlist of area distributions for each of the set of functions. The netlist can be used to synthesize a set of cell libraries wherein an N-diffusion to P-diffusion area allowance is varied among the set of cell libraries. Thereafter, the method may also include comparing a time delay associated with each of the set of cell libraries with a time delay of a library benchmark delay. Based on the comparing, a delay number may be associated with each of the cell libraries. Finally, the cell libraries may be ranked based on the respective delay numbers associated with each of the cell libraries.

    摘要翻译： 提供了一种用于提供高速单元库的方法。 该方法可以包括例如选择一组常见的逻辑功能。 该方法然后可以包括获得每组功能的区域分布的网表。 网表可以用于合成一组细胞库，其中在扩增区域的N扩散面积允许量在该组细胞库之间是变化的。 此后，该方法还可以包括将与该组单元库中的每一个相关联的时间延迟与库基准延迟的时间延迟进行比较。 基于比较，延迟数可以与每个单元库相关联。 最后，可以基于与每个细胞库相关联的相应的延迟数来对细胞库进行排名。