公开(公告)号：US5177031A

公开(公告)日：1993-01-05

申请号：US707557

申请日：1991-05-30

申请人： Peter L. Buchmann ,  David J. Webb ,  Peter Vettiger

发明人： Peter L. Buchmann ,  David J. Webb ,  Peter Vettiger

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01S5/00 ,  H01S5/02 ,  H01S5/028

CPC分类号： H01L21/02052 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02307 ,  H01L21/314 ,  H01L21/31616 ,  H01L21/3185 ,  H01S5/028 ,  H01S5/0203 ,  H01S5/0282 ,  Y10S438/958

摘要： A method of passivating etched mirror facets of semiconductor laser diodes which enhances device reliability.The etched mirror facet is first subjected to a weet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

摘要翻译： 钝化半导体激光二极管的蚀刻镜面的方法，这增强了器件的可靠性。 蚀刻的镜面首先经受蚀刻蚀刻工艺，以基本上除去任何自然氧化物以及在前面的镜蚀刻工艺期间可能被机械损坏的任何表面层。 然后，施加钝化预处理，由此除去任何残留的氧，并且形成亚单层，其永久地减少在镜面处的少数载流子的非辐射复合。 最后，预处理的镜面涂有钝化层，以避免对镜子产生任何环境影响。

公开(公告)号：US5032219A

公开(公告)日：1991-07-16

申请号：US533748

申请日：1990-06-06

申请人： Peter L. Buchmann ,  Peter Vettiger ,  Otto Voegeli ,  David J. Webb

发明人： Peter L. Buchmann ,  Peter Vettiger ,  Otto Voegeli ,  David J. Webb

IPC分类号： H01L21/302 ,  G02B6/122 ,  H01L21/3065 ,  H01L27/15 ,  H01S5/00 ,  H01S5/02 ,  H01S5/028 ,  H01S5/16 ,  H01S5/22

CPC分类号： H01S5/22 ,  H01S5/028 ,  H01S5/16 ,  H01S5/0202 ,  H01S5/0203

摘要： A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

公开(公告)号：US5103493A

公开(公告)日：1992-04-07

申请号：US669817

申请日：1991-03-15

申请人： Peter L. Buchmann ,  Peter Vettiger ,  Otto Voegeli ,  David J. Webb

发明人： Peter L. Buchmann ,  Peter Vettiger ,  Otto Voegeli ,  David J. Webb

IPC分类号： H01L21/302 ,  G02B6/122 ,  H01L21/3065 ,  H01L27/15 ,  H01S5/00 ,  H01S5/02 ,  H01S5/028 ,  H01S5/16 ,  H01S5/22

CPC分类号： H01S5/22 ,  H01S5/028 ,  H01S5/16 ,  H01S5/0202 ,  H01S5/0203

摘要： A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

摘要翻译： 一种用于改进具有非平面条纹波导的集成光学结构的蚀刻镜面18（例如脊或沟槽二极管激光器）或无源器件（诸如调制器和开关）的平面度的方法和装置。 由于地形，光刻和蚀刻过程效应，波导边缘处的镜面表面的曲率造成有害的相位失真，并且通过加宽靠近镜面的波导端来避免，从而使弯曲的小面区域远离光线 模式区域到曲面不重要的表面区域。

公开(公告)号：US4803181A

公开(公告)日：1989-02-07

申请号：US26799

申请日：1987-03-17

申请人： Peter L. Buchmann ,  Peter Vettiger ,  Bart J. Van Zeghbroech

发明人： Peter L. Buchmann ,  Peter Vettiger ,  Bart J. Van Zeghbroech

IPC分类号： H01L21/30 ,  G03F7/40 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/265

CPC分类号： G03F7/405 ,  Y10S148/051 ,  Y10S148/111 ,  Y10S148/137 ,  Y10S438/947 ,  Y10S438/948 ,  Y10S438/949 ,  Y10S438/95

摘要： A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions.First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.

摘要翻译： 用于形成用于制造半导体结构的侧壁的方法，其中薄的垂直侧壁被“图像转印”以限定亚微米横向尺寸。 首先，在其上将形成侧壁的基板上形成具有基本垂直边缘的图案化抗蚀剂轮廓。 然后，将该轮廓浸泡在反应性有机金属硅烷化剂中以将抗蚀剂的顶部和垂直边缘甲硅烷化至预定深度，从而使轮廓表面具有高耐氧蚀刻性。 在随后的各向异性RIE过程中，去除了甲硅烷基化曲线和未磺酰化的抗蚀剂的水平表面，留下提供所需的独立侧壁的甲硅烷基化的垂直边缘基本上不受影响。

公开(公告)号：US4732871A

公开(公告)日：1988-03-22

申请号：US31648

申请日：1987-03-30

申请人： Peter L. Buchmann ,  Volker Graf ,  Peter D. Hoh ,  Theodor O. Mohr ,  Peter Vettiger

发明人： Peter L. Buchmann ,  Volker Graf ,  Peter D. Hoh ,  Theodor O. Mohr ,  Peter Vettiger

IPC分类号： H01L21/033 ,  H01L21/285 ,  H01L21/311 ,  H01L21/318 ,  H01L21/336 ,  H01L21/338 ,  H01L29/812 ,  H01L21/265

CPC分类号： H01L29/66871 ,  H01L21/0337 ,  H01L21/28587 ,  H01L21/31111 ,  H01L21/3185 ,  H01L29/66545

摘要： Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.

公开(公告)号：US5032879A

公开(公告)日：1991-07-16

申请号：US536828

申请日：1990-06-11

申请人： Peter L. Buchmann ,  Christoph S. Harder ,  Otto Vogeli

发明人： Peter L. Buchmann ,  Christoph S. Harder ,  Otto Vogeli

IPC分类号： H01S5/00 ,  H01L33/00 ,  H01S5/026 ,  H01S5/10 ,  H01S5/14

CPC分类号： H01S5/0264 ,  H01S5/0042 ,  H01S5/1082 ,  H01S5/14

摘要： An integrated semiconductor structure with optically coupled laser diode (11) and photodiode 12A, both devices having etched, vertical facets (16A, 21). The photodiode has a spatially non-uniform sensitivity profile with respect to the incident light beam (18A) emitted by the laser. This is due to the varying distance from the laser facet and/or to variations in the angle of incidence and results in photocurrents produced by the photodiode that depend on the intensity distribution of the light beam. The spatially non-uniform sensitivity profile allows the measurement of the far-field intensity distribution of the laser and thus on-wafer screening of lasers with respect to their mode stability.

公开(公告)号：US20100005281A1

公开(公告)日：2010-01-07

申请号：US12166139

申请日：2008-07-01

申请人： Peter L. Buchmann ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert J. Reese ,  Eric E. Retter ,  Martin L. Schmatz ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

发明人： Peter L. Buchmann ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert J. Reese ,  Eric E. Retter ,  Martin L. Schmatz ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

IPC分类号： G06F9/24

CPC分类号： G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

公开(公告)号：US08139430B2

公开(公告)日：2012-03-20

申请号：US12166139

申请日：2008-07-01

申请人： Peter L. Buchmann ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert J. Reese ,  Eric E. Retter ,  Martin L. Schmatz ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

发明人： Peter L. Buchmann ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert J. Reese ,  Eric E. Retter ,  Martin L. Schmatz ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

IPC分类号： G11C7/10 ,  G11C7/18

CPC分类号： G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。