公开(公告)号：US4732871A

公开(公告)日：1988-03-22

申请号：US31648

申请日：1987-03-30

申请人： Peter L. Buchmann ,  Volker Graf ,  Peter D. Hoh ,  Theodor O. Mohr ,  Peter Vettiger

发明人： Peter L. Buchmann ,  Volker Graf ,  Peter D. Hoh ,  Theodor O. Mohr ,  Peter Vettiger

IPC分类号： H01L21/033 ,  H01L21/285 ,  H01L21/311 ,  H01L21/318 ,  H01L21/336 ,  H01L21/338 ,  H01L29/812 ,  H01L21/265

CPC分类号： H01L29/66871 ,  H01L21/0337 ,  H01L21/28587 ,  H01L21/31111 ,  H01L21/3185 ,  H01L29/66545

摘要： Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.

公开(公告)号：US4647954A

公开(公告)日：1987-03-03

申请号：US654707

申请日：1984-09-27

申请人： Volker Graf ,  Pierre L. Gueret ,  Carl A. Mueller

发明人： Volker Graf ,  Pierre L. Gueret ,  Carl A. Mueller

IPC分类号： H01L29/15 ,  H01L39/22 ,  H01L29/78

CPC分类号： H01L39/228 ,  H01L29/157 ,  Y10S505/86

摘要： The transistor comprises two electrodes, source (12) and drain (13), with a semiconductor tunnel channel (11) arranged therebetween. A gate (14) for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier (some meV) through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage V.sub.G which modifies the barrier height between source and drain thereby changing the tunnel probability.

摘要翻译： 晶体管包括两个电极，源极（12）和漏极（13），其间布置有半导体隧道通道（11）。 用于施加控制信号的门（14）耦合到通道。 半导体在低温下的行为就像具有低势垒（一些meV）的绝缘体，电荷载体可以在所施加的漏极电压的影响下隧穿。 隧道电流可以通过栅极电压VG来控制，栅极电压VG改变源极和漏极之间的势垒高度，从而改变隧道概率。

公开(公告)号：US5037776A

公开(公告)日：1991-08-06

申请号：US407507

申请日：1989-09-14

申请人： Yvan Galeuchet ,  Volker Graf ,  Wilhelm Heuberger ,  Peter Roentgen

发明人： Yvan Galeuchet ,  Volker Graf ,  Wilhelm Heuberger ,  Peter Roentgen

IPC分类号： H01L29/201 ,  C30B29/40 ,  H01L21/20 ,  H01L21/205 ,  H01L21/338 ,  H01L29/775 ,  H01L29/812 ,  H01S5/12 ,  H01S5/223 ,  H01S5/227 ,  H01S5/30 ,  H01S5/32 ,  H01S5/323 ,  H01S5/34 ,  H01S5/40

CPC分类号： B82Y20/00 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02433 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/775 ,  H01S5/323 ,  H01S5/34 ,  H01S5/1228 ,  H01S5/2238 ,  H01S5/2275 ,  H01S5/305 ,  H01S5/3202 ,  H01S5/3428 ,  H01S5/4031 ,  Y10S148/065 ,  Y10S148/095

摘要： A method, and devices produced therewith, for the epitaxial growth of sub-micron semiconductor structures with at least one crystal plane-dependently grown, buried active layer (24) consisting of a III-V compound. The active layer (24) and adjacent embedding layers (23, 25) form a heterostructure produced in a one-step growth process not requiring removal of the sample from the growth chamber in between layer depositions. The layers of the structure are grown on a semiconductor substrate (21) having a structured surface exposing regions of different crystal orientation providing growth and no-growth-planes for the selective growth process. The method allows the production of multiple, closely spaced active layers and of layers consisting of adjoining sections having different physical properties.

公开(公告)号：US4728621A

公开(公告)日：1988-03-01

申请号：US934372

申请日：1986-11-24

申请人： Volker Graf ,  Albertus Oosenbrug

发明人： Volker Graf ,  Albertus Oosenbrug

IPC分类号： H01L29/812 ,  H01L21/336 ,  H01L21/338 ,  H01L21/265 ,  H01L21/285

CPC分类号： H01L29/66871 ,  H01L29/66545

摘要： A process for the fabrication of "low temperature"-gate MESFET structures, i.e., gate metal deposition takes place after annealing of an n.sup.+ -implant that form source- and drain- contact regions. The process permits self-alignment of all three important MESFET parts, namely, the implanted contact regions, and both, the ohmic, as well as the gate, contact metallizations. In the process, a multi-layer "inverted-T" structure is used as a mask for the n.sup.+ -implant and for the ohmic and gate metallizations. The upper part of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer of the "inverted-T", the shoulders being obtained using sidewall techniques.

摘要翻译： 用于制造“低温”门MESFET结构的方法，即栅极金属沉积在形成源极和漏极 - 接触区域的n + - 植入物退火之后进行。 该过程允许所有三个重要的MESFET部件，即注入接触区域以及欧姆以及栅极接触金属化两者的自对准。 在此过程中，使用多层“反转T”结构作为n +种植体和欧姆和栅极金属化的掩模。 “反转T”的上部是所谓的虚拟栅极，在欧姆接触金属沉积之后被肖特基门代替。 源栅极和漏极 - 栅极分离由“倒T”的下层的肩部确定，肩部使用侧壁技术获得。

公开(公告)号：US5938295A

公开(公告)日：1999-08-17

申请号：US584943

申请日：1996-01-16

申请人： Werner Stumpe ,  Andreas Schlichenmaier ,  Heinz Kaechele ,  Volker Graf ,  Bernhard Schwendemann ,  Juergen Wrede

发明人： Werner Stumpe ,  Andreas Schlichenmaier ,  Heinz Kaechele ,  Volker Graf ,  Bernhard Schwendemann ,  Juergen Wrede

IPC分类号： B60T8/18 ,  B60T8/1766 ,  B60T8/26 ,  B60T13/68

CPC分类号： B60T8/1766 ,  B60T13/683 ,  B60T8/266

摘要： An electronic control unit adjusts the pressure in the brake cylinders of at least one axle during the braking process on the basis of measured static and dynamic loads at the other axle.

摘要翻译： 电子控制单元在制动过程中根据测量的另一个轴上的静态和动态负载来调节至少一个轴的制动缸中的压力。

公开(公告)号：US5439876A

公开(公告)日：1995-08-08

申请号：US108138

申请日：1993-08-16

申请人： Volker Graf ,  Carl A. Mueller

发明人： Volker Graf ,  Carl A. Mueller

IPC分类号： C30B23/08 ,  C01G1/00 ,  C23C14/08 ,  C23C14/24 ,  C30B25/02 ,  C30B29/22 ,  H01B12/00 ,  H01B13/00 ,  H01L39/12 ,  H01L39/24 ,  C30B19/10 ,  C01F11/00

CPC分类号： B82Y30/00 ,  C30B25/02 ,  C30B29/68 ,  H01L39/126 ,  H01L39/2458

摘要： A method for making layered structures of artificial high T.sub.c superconductor compounds by which on top of a seed crystal having a lattice structure matching the lattice structure of the superconductor compound to be made, oxide layers of all constituent components are epitaxially grown in a predetermined sequence so as to create a sandwich structure not found in natural crystals. The epitaxial deposition of the constituent components is performed in a reaction chamber having evaporation facilities, inlets for metal-organic gases, and inlets for background gases including oxygen.

摘要翻译： 制造人造高Tc超导体化合物的层状结构的方法，其中在具有与要制备的超导体化合物的晶格结构匹配的晶格结构的晶种的顶部上，以预定的顺序外延生长所有构成组分的氧化物层， 以产生在天然晶体中未发现的夹心结构。 构成组分的外延沉积在具有蒸发设备，金属有机气体入口和包括氧气的背景气体入口的反应室中进行。