公开(公告)号：US08518811B2

公开(公告)日：2013-08-27

申请号：US13082793

申请日：2011-04-08

申请人： Philipp Riess ,  Domagoj Siprak

发明人： Philipp Riess ,  Domagoj Siprak

IPC分类号： H01L21/312

CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/872 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

摘要翻译： 在一个实施例中，半导体器件包括设置在衬底的第一区域中的第一掺杂区域。 具有金属层的第一部分的第一金属电极设置在第一掺杂区域上并与第一掺杂区域接触。 第二掺杂区域设置在衬底的第二区域中。 电介质层设置在第二掺杂区上。 具有金属层的第二部分的第二金属电极设置在介电层上。 第二金属电极电容耦合到第二掺杂区域。

公开(公告)号：US20120256274A1

公开(公告)日：2012-10-11

申请号：US13082793

申请日：2011-04-08

申请人： Philipp Riess ,  Domagoj Siprak

发明人： Philipp Riess ,  Domagoj Siprak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/48

CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/872 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

摘要翻译： 在一个实施例中，半导体器件包括设置在衬底的第一区域中的第一掺杂区域。 具有金属层的第一部分的第一金属电极设置在第一掺杂区域上并与第一掺杂区域接触。 第二掺杂区域设置在衬底的第二区域中。 电介质层设置在第二掺杂区上。 具有金属层的第二部分的第二金属电极设置在介电层上。 第二金属电极电容耦合到第二掺杂区域。

公开(公告)号：US08860225B2

公开(公告)日：2014-10-14

申请号：US13271878

申请日：2011-10-12

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/316 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US20130240884A1

公开(公告)日：2013-09-19

申请号：US13729145

申请日：2012-12-28

申请人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

发明人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

IPC分类号： H01L23/544 ,  H01L27/04

CPC分类号： H01L23/544 ,  H01L23/562 ,  H01L23/642 ,  H01L27/04 ,  H01L2224/16225

摘要： A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

摘要翻译： 描述了可以可重复地测量微小电容及其变化的电容传感器和测量电路。 电容可以根据当地的环境条件（例如机械应力（例如翘曲或剪切应力）），机械压力，温度和/或湿度而变化。 可能需要提供集成到半导体芯片中的电容器，该电容器足够小并且敏感以准确地测量半导体芯片预期经历的条件。

公开(公告)号：US20120099243A1

公开(公告)日：2012-04-26

申请号：US13344714

申请日：2012-01-06

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01G4/005

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US20050003564A1

公开(公告)日：2005-01-06

申请号：US10866863

申请日：2004-06-14

申请人： Silke Bargstadt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Silke Bargstadt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L23/544 ,  H01L23/60 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

摘要翻译： 用于确定集成电路的ESD /闭锁强度的方法包括使用相同的制造工艺制造集成电路和测试结构。 测量测试结构的电气参数，并且从测量的参数值导出与集成电路相关联的特征值，其中特征值表征与集成电路相关联的ESD或闭锁特性曲线。 该方法还包括测试每种情况下的特征值是否在分配给它们的预定范围内，其中选择范围使得如果每种情况下的特征值在其范围内，则存在期望的ESD /闩锁强度。

公开(公告)号：US09793220B2

公开(公告)日：2017-10-17

申请号：US13729145

申请日：2012-12-28

申请人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

发明人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

IPC分类号： G01R31/3187 ,  G01R31/26 ,  H01L23/544 ,  H01L27/04 ,  H01L23/00 ,  H01L23/64

CPC分类号： H01L23/544 ,  H01L23/562 ,  H01L23/642 ,  H01L27/04 ,  H01L2224/16225

摘要： A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

公开(公告)号：US08569820B2

公开(公告)日：2013-10-29

申请号：US13344714

申请日：2012-01-06

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01L27/108

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US20120091560A1

公开(公告)日：2012-04-19

申请号：US13334768

申请日：2011-12-22

申请人： Philipp Riess ,  Armin Fischer

发明人： Philipp Riess ,  Armin Fischer

IPC分类号： H01L29/92 ,  H01G4/018

CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

摘要： Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.

摘要翻译： 公开了形成理想MIM电容器的结构和方法。 单个电容器包括覆盖衬底的第一和第二金属结构，设置在第一金属结构的第一部分和第二金属结构的第一部分之间的第一介电材料。 第二介电材料设置在第一金属结构的第二部分和第二金属结构的第二部分之间。 在第一和第二金属结构的第二部分之间没有设置第一介电材料，并且在第一和第二金属结构的第一部分之间没有设置第二介电材料。 第一和第二介电材料层包括具有相反的电容系数的材料。

公开(公告)号：US20120025382A1

公开(公告)日：2012-02-02

申请号：US13271878

申请日：2011-10-12

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/532 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。