公开(公告)号：US09379201B2

公开(公告)日：2016-06-28

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L21/4763 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L21/768 ,  H01L29/872 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/304 ,  H01L23/48 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20140306349A1

公开(公告)日：2014-10-16

申请号：US13861086

申请日：2013-04-11

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Urmi Ray ,  Roawen Chen ,  Brian Matthew Henderson ,  Ratibor Radojcic ,  Matthew Nowak ,  Nicholas Yu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.

Abstract translation: 一些实施方案提供了一种插入器，其包括衬底，衬底中的通孔和氧化层。 通孔包括金属材料。 氧化层位于通孔和衬底之间。 在一些实施方式中，衬底是硅衬底。 在一些实施方案中，氧化层是通过将基底暴露于热而形成的热氧化物。 在一些实施方案中，氧化层被配置为在通孔和基底之间提供电绝缘。 在一些实施方案中，插入件还包括绝缘层。 在一些实施方案中，绝缘层是聚合物层。 在一些实现中，插入器还包括在插入器的表面上的至少一个互连。 所述至少一个互连件位于所述插入件的表面上，使得所述氧化层位于所述互连件和所述基板之间。

公开(公告)号：US20130302943A1

公开(公告)日：2013-11-14

申请号：US13945722

申请日：2013-07-18

Applicant: QUALCOMM Incorporated

Inventor： Arvind Chandrasekaran ,  Brian Matthew Henderson

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/525 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract translation: 可以制造堆叠集成电路（IC），其具有结合到双面第一层晶片的第二层晶片。 双面第一层晶片在晶片的正面和背面包括后端（BEOL）层。 第一层晶圆内的扩展触点连接前侧和后侧BEOL层。 延伸的接触延伸穿过第一层晶片的结。 第二层晶片通过延伸的触点耦合到第一层晶片的前侧。 附加触点将第一层晶片内的器件与前端BEOL层耦合。 当在堆叠的IC中使用双面晶片时，堆叠的IC的高度可能会降低。 堆叠的IC可以包括具有相同功能的晶片或具有不同功能的晶片。

公开(公告)号：US20150333053A1

公开(公告)日：2015-11-19

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L27/02 ,  H01L23/48 ,  H01L29/66 ,  H01L21/304 ,  H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/768 ,  H01L29/872

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20150048497A1

公开(公告)日：2015-02-19

申请号：US13968708

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Brian Matthew Henderson ,  Shiqun Gu ,  Urmi Ray

IPC: H01L23/498 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L23/60 ,  H01L31/0443 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  Y02E10/50

Abstract: A photovoltaic (PV) substrate includes a grooved die-facing surface to form a channel for a bypass diode. The die-facing surface supports a screen-printed metal interconnect layer to form a first terminal for the bypass diode.

Abstract translation: 光伏（PV）衬底包括沟槽的面对芯片的表面，以形成旁路二极管的通道。 面向芯片的表面支撑丝网印刷金属互连层，以形成用于旁路二极管的第一端子。

公开(公告)号：US08912043B2

公开(公告)日：2014-12-16

申请号：US13945722

申请日：2013-07-18

Applicant: QUALCOMM Incorporated

Inventor： Arvind Chandrasekaran ,  Brian Matthew Henderson

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/50 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/525 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract translation: 可以制造堆叠集成电路（IC），其具有结合到双面第一层晶片的第二层晶片。 双面第一层晶片在晶片的正面和背面包括后端（BEOL）层。 第一层晶圆内的扩展触点连接前侧和后侧BEOL层。 延伸的接触延伸穿过第一层晶片的结。 第二层晶片通过延伸的触点耦合到第一层晶片的前侧。 附加触点将第一层晶片内的器件与前端BEOL层耦合。 当在堆叠的IC中使用双面晶片时，堆叠的IC的高度可能会降低。 堆叠的IC可以包括具有相同功能的晶片或具有不同功能的晶片。

公开(公告)号：US20140225246A1

公开(公告)日：2014-08-14

申请号：US14133451

申请日：2013-12-18

Applicant: QUALCOMM INCORPORATED

Inventor： Brian Matthew Henderson ,  Durodami Joscelyn Lisk ,  Shiqun Gu ,  Ratibor Radojcic ,  Matthew Michael Nowak

IPC: H01L23/538 ,  H01L23/36

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5286 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.

Abstract translation: 一些实施方案提供了集成器件，其包括第一衬底，耦合到第一衬底的第一裸片，耦合到第一裸片的第二裸片以及耦合到第二裸片的第二衬底。 第二基板被配置为提供用于到第二管芯的信号的电路径。 集成装置还包括围绕第一管芯和第二管芯的模制件以及耦合到第二衬底的多个通孔模具通孔（TMV）。 TMV被配置为提供通过第二基板的信号到第二管芯的电路径。 在一些实施方案中，第二衬底包括被配置为向第二裸片提供信号的电路的信号分配结构。 在一些实施方案中，第一衬底和第二衬底是向第二裸片提供信号的信号分配网络的一部分。