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    BAD BLOCK MANAGEMENT MECHANISM
    2.
    发明申请
    BAD BLOCK MANAGEMENT MECHANISM 有权
    边框管理机制

    公开(公告)号：US20140006848A1

    公开(公告)日：2014-01-02

    申请号：US13537969

    申请日：2012-06-29

    申请人： RAJ K. RAMANUJAN ,  Glenn J. Hinton ,  David J. Zimmerman

    发明人： RAJ K. RAMANUJAN ,  Glenn J. Hinton ,  David J. Zimmerman

    IPC分类号： G11B20/18

    CPC分类号： G11B20/1883 ,  G11C29/82 ,  G11C29/886

    摘要： A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.

    摘要翻译： 一种系统包括非易失性随机存取存储器（NVRAM）装置和控制器逻辑，用于检测装置内的坏块，通过将坏块的地址分配给替换来退出坏块并用替换块替换坏块 块。

    Method and system for error management in a memory device
    6.
    发明授权
    Method and system for error management in a memory device 有权
    存储器件中错误管理的方法和系统

    公开(公告)号：US09158616B2

    公开(公告)日：2015-10-13

    申请号：US13619452

    申请日：2012-09-14

    申请人： Kuljit S. Bains ,  David J. Zimmerman ,  Dennis W. Brzezinski ,  Michael Williams ,  John B. Halbert

    发明人： Kuljit S. Bains ,  David J. Zimmerman ,  Dennis W. Brzezinski ,  Michael Williams ,  John B. Halbert

    IPC分类号： G06F11/00 ,  G06F11/10

    CPC分类号： G06F11/10 ,  G06F11/1016

    摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

    摘要翻译： 一种用于存储器件中的错误管理的方法和系统。 在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。 在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。 如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

    Method and system for error management in a memory device
    7.
    发明授权
    Method and system for error management in a memory device 有权
    存储器件中错误管理的方法和系统

    公开(公告)号：US08862973B2

    公开(公告)日：2014-10-14

    申请号：US12634286

    申请日：2009-12-09

    申请人： Kuljit S. Bains ,  David J. Zimmerman ,  Dennis W. Brzezinski ,  Michael Williams ,  John B. Halbert

    发明人： Kuljit S. Bains ,  David J. Zimmerman ,  Dennis W. Brzezinski ,  Michael Williams ,  John B. Halbert

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1016

    摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

    摘要翻译： 一种用于存储器件中的错误管理的方法和系统。 在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。 在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。 如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

    Low speed access to DRAM
    8.
    发明授权
    Low speed access to DRAM 失效

    公开(公告)号：US08619883B2

    公开(公告)日：2013-12-31

    申请号：US12583920

    申请日：2009-08-24

    申请人： David J. Zimmerman ,  Michael W. Williams

    发明人： David J. Zimmerman ,  Michael W. Williams

    IPC分类号： H04B3/00 ,  H04L25/00

    CPC分类号： G06F13/28 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096

    摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

    Boundary scan chain for stacked memory
    9.
    发明授权
    Boundary scan chain for stacked memory 有权
    用于堆叠内存的边界扫描链

    公开(公告)号：US08645777B2

    公开(公告)日：2014-02-04

    申请号：US13340470

    申请日：2011-12-29

    申请人： David J. Zimmerman

    发明人： David J. Zimmerman

    IPC分类号： G01R31/28

    CPC分类号： G11C29/32 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G11C5/04 ,  G11C11/4087 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

    摘要翻译： 堆叠式存储器的边界扫描链。 存储器件的实施例包括系统元件和包括一个或多个存储管芯层的存储器堆叠，每个存储器管芯层包括用于I / O单元的输入输出（I / O）单元和边界扫描链。 存储芯片层的边界扫描链包括用于每个I / O单元的扫描链部分，用于I / O单元的扫描链部分包括第一扫描逻辑多路复用器，扫描逻辑锁存器，扫描逻辑的输入 锁存器与第一扫描逻辑多路复用器的输出耦合，以及解码器，用于向边界扫描链提供命令信号。