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公开(公告)号：US09189331B2
公开(公告)日：2015-11-17
申请号：US13247234
申请日：2011-09-28
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , G06F13/16 , G06F13/18 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02 , G06F12/12 , G06F13/364
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.
摘要翻译： 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。
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2.发明授权Requester based transaction status reporting in a system with multi-level memory 有权在具有多级内存的系统中基于请求者的事务状态报告公开(公告)号：US08732416B2
公开(公告)日：2014-05-20
申请号：US13239045
申请日：2011-09-21
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.
摘要翻译： 系统具有可由中央处理单元（CPU）访问的存储器资源。 一个或多个事务请求由CPU启动以访问一个或多个存储器资源。 交易请求的启动停止一段时间。 监视内存资源，以确定CPU启动的所有事务请求何时完成。 提供由CPU访问的空闲信号，当由CPU发起的所有事务请求已经完成时，该信号被断言。
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公开(公告)号：US20120198164A1
公开(公告)日：2012-08-02
申请号：US13247234
申请日：2011-09-28
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write- back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.
摘要翻译： 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。
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4.发明申请Requester Based Transaction Status Reporting in a System with Multi-Level Memory 有权具有多级内存的系统中基于请求者的事务状态报告公开(公告)号：US20120079102A1
公开(公告)日：2012-03-29
申请号：US13239045
申请日：2011-09-21
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.
摘要翻译： 系统具有可由中央处理单元（CPU）访问的存储器资源。 一个或多个事务请求由CPU启动以访问一个或多个存储器资源。 交易请求的启动停止一段时间。 监视内存资源，以确定CPU启动的所有事务请求何时完成。 提供由CPU访问的空闲信号，当由CPU发起的所有事务请求已经完成时，该信号被断言。
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公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译： 并行流水线用于访问共享内存。 通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。 通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。 维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。 在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。
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公开(公告)号：US08560896B2
公开(公告)日：2013-10-15
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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7.发明授权公开(公告)号：US08970267B2
公开(公告)日：2015-03-03
申请号：US12874627
申请日：2010-09-02
摘要： This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.
摘要翻译： 本发明是明确地确定在设计中使用的各种时钟沿的发生的一种手段，平衡集成电路内的各个位置处的时钟沿。 从外部源进入的时钟可能是片上变化（OCV）的来源，导致不可接受的时钟边缘偏移。 本发明将各种时钟分频器布置在使用这些时钟的远程位置的芯片上。 这最小化边缘发生的不确定性。
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8.发明授权Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines 有权可配置的基于源/请求者的错误检测和纠正多级缓存中的软错误，以最大限度地减少CPU中断服务程序公开(公告)号：US08707127B2
公开(公告)日：2014-04-22
申请号：US13243335
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
IPC分类号： H03M13/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
摘要翻译： 本发明是一种具有奇偶生成的存储器系统，其选择性地形成并存储对应的多个数据源的奇偶校验位。 奇偶生成和存储取决于全局挂起位和全局使能位的状态，以及与每个数据源相对应的奇偶校验检测/校正。
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9.发明申请ENHANCED PIPELINING AND MULTI-BUFFER ARCHITECTURE FOR LEVEL TWO CACHE CONTROLLER TO MINIMIZE HAZARD STALLS AND OPTIMIZE PERFORMANCE 有权提高两级缓存控制器的管道和多缓冲结构，最大限度地减少危害和优化性能公开(公告)号：US20120260031A1
公开(公告)日：2012-10-11
申请号：US13245211
申请日：2011-09-26
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.
摘要翻译： 本发明是包括中央处理单元，外部接口，一级缓存，包括二级统一缓存的二级存储器和直接可寻址存储器的数据处理系统。 二级存储器控制器包括可直接寻址的存储器读取流水线，中央处理单元写入流水线，外部可缓存流水线和外部非缓存流水线。
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公开(公告)号：US20120198272A1
公开(公告)日：2012-08-02
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/16
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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