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    RESISTIVE MEMORY AND METHODS FOR FORMING SAME
    1.
    发明申请
    RESISTIVE MEMORY AND METHODS FOR FORMING SAME 审中-公开
    电阻记忆及其形成方法

    公开(公告)号：US20090190388A1

    公开(公告)日：2009-07-30

    申请号：US12019364

    申请日：2008-01-24

    申请人： Rainer Bruchhaus ,  Ulrike Gruening Von Schwerin

    发明人： Rainer Bruchhaus ,  Ulrike Gruening Von Schwerin

    IPC分类号： G11C11/00 ,  H01L21/20

    CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

    摘要： A method of fabricating a resistive storage device is provided. The method generally comprises providing an electrode structure stack comprising a first electrode and an electrode structure mask arranged at the first electrode, forming a support structure at least partly at the electrode structure mask, removing the electrode structure mask to leave a storage region window in the support structure, and forming a resistive storage region in the storage region window at the first electrode.

    摘要翻译： 提供一种制造电阻存​​储装置的方法。 该方法通常包括提供包括布置在第一电极处的第一电极和电极结构掩模的电极结构堆叠，至少部分地形成在电极结构掩模处的支撑结构，去除电极结构掩模以将存储区窗口留在 并且在第一电极的存储区窗口中形成电阻存储区。

    Process for fabrication of a ferroelectric capacitor
    4.
    发明授权
    Process for fabrication of a ferroelectric capacitor 失效
    铁电电容器制造工艺

    公开(公告)号：US07199002B2

    公开(公告)日：2007-04-03

    申请号：US10651614

    申请日：2003-08-29

    申请人： Karl Hornik ,  Rainer Bruchhaus ,  Nicolas Nagel

    发明人： Karl Hornik ,  Rainer Bruchhaus ,  Nicolas Nagel

    IPC分类号： H01L27/108

    CPC分类号： H01L28/56 ,  H01L21/31616 ,  H01L21/31683

    摘要： A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.

    摘要翻译： 一种用于制造铁电电容器的方法，包括在Al 2 O 3 3的绝缘层3上沉积Ti 5层，并氧化Ti层以形成TiO 然后，在TiO 2层7上形成PZT 9层.PZT层9经历退火步骤，其中由于 TiO 2层7的存在使其结晶形成具有高度（111） - 纹理的层11。

    Ferroelectric memory arrangement
    5.
    发明申请
    Ferroelectric memory arrangement 失效
    铁电存储器布置

    公开(公告)号：US20060049440A1

    公开(公告)日：2006-03-09

    申请号：US11216678

    申请日：2005-08-31

    申请人： Rainer Bruchhaus ,  Martin Gutsche ,  Cay-Uwe Pinnow

    发明人： Rainer Bruchhaus ,  Martin Gutsche ,  Cay-Uwe Pinnow

    IPC分类号： H01L29/94

    CPC分类号： G11C11/22 ,  G11C11/221 ,  H01L27/11502 ,  H01L27/11507

    摘要： A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

    摘要翻译： 具有存储单元的铁电存储器装置，其中每个具有垂直电极和垂直电极之间的铁电电介质的垂直铁电存储电容器连接到选择晶体管，铁电介质在多个铁电层之间， 其布置有绝缘分离层。

    Memory cell configuration and method for its production
    8.
    发明授权
    Memory cell configuration and method for its production 失效
    存储单元配置及其生产方法

    公开(公告)号：US06300652B1

    公开(公告)日：2001-10-09

    申请号：US08755456

    申请日：1996-11-22

    申请人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    发明人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    IPC分类号： H01L27108

    CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

    摘要： A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.

    摘要翻译： 存储单元配置及其制造方法包括堆叠电容器，并且使用具有铁电或顺电存储电介质的垂直存储电容器。 为了制造存储电容器，在整个区域上产生用于存储电介质的电介质层。 随后构造电介质层，形成用于存储电容器的第一电极和第二电极。 本发明适用于Gbit DRAM和非易失性存储器。

    Method for nondestructively reading resistive memory elements
    9.
    发明授权
    Method for nondestructively reading resistive memory elements 有权
    无损读取电阻式存储器元件的方法

    公开(公告)号：US09001558B2

    公开(公告)日：2015-04-07

    申请号：US14000285

    申请日：2012-02-03

    申请人： Roland Daniel Rosezin ,  Florian Lentz ,  Rainer Bruchhaus ,  Eike Linn ,  Ilia Valov ,  Rainer Waser ,  Stefan Tappertzhofen ,  Lutz Nielen

    发明人： Roland Daniel Rosezin ,  Florian Lentz ,  Rainer Bruchhaus ,  Eike Linn ,  Ilia Valov ,  Rainer Waser ,  Stefan Tappertzhofen ,  Lutz Nielen

    IPC分类号： G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0073 ,  G11C2213/73 ,  G11C2213/76

    摘要： A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.

    摘要翻译： 读出存储元件的方法包括串联连接。 至少两个存储单元A和B各自具有具有较高电阻的稳定状态A0或B0以及具有较低电阻的稳定状态A1或B1。 测量串联电路的电变量，并为此测量选择电变量，状态A0中的存储单元A与状态B0中的存储单元B和/或存储单元A设置的存储单元A的贡献不同 A1在状态B1中与存储单元B的贡献不同。 两个状态组合A1和B0或A0和B1然后导致通过串联电路测量的电变量的不同值。 因此，这些状态组合可以彼此区分，而不必在读取期间改变存储元件的逻辑状态。