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8 条记录 (耗时 0.046 秒)

    Power management apparatus, systems, and methods
    4.
    发明申请
    Power management apparatus, systems, and methods 失效
    电源管理装置，系统和方法

    公开(公告)号：US20050289366A1

    公开(公告)日：2005-12-29

    申请号：US10880976

    申请日：2004-06-29

    申请人： Patrick Reilly

    发明人： Patrick Reilly

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

    摘要： Apparatus and systems, as well as methods and articles, may operate to compare a set of desired power states associated with components included in an applications subsystem and one or more operations with a set of actual power states. The set of actual power states may be adjusted according to a function that depends on the set of desired power states.

    摘要翻译： 设备和系统以及方法和物品可以操作以将与应用子系统中包括的组件和一个或多个操作相关联的一组期望功率状态与一组实际功率状态进行比较。 可以根据取决于所需功率状态的集合的功能来调整实际功率状态的集合。

    Planarizing etch hardmask to increase pattern density and aspect ratio
    5.
    发明授权
    Planarizing etch hardmask to increase pattern density and aspect ratio 失效
    平铺蚀刻硬掩模以增加图案密度和纵横比

    公开(公告)号：US08513129B2

    公开(公告)日：2013-08-20

    申请号：US12790203

    申请日：2010-05-28

    申请人： Martin Jay Seamons ,  Kwangduk Douglas Lee ,  Chiu Chan ,  Patrick Reilly ,  Sudha Rathi

    发明人： Martin Jay Seamons ,  Kwangduk Douglas Lee ,  Chiu Chan ,  Patrick Reilly ,  Sudha Rathi

    IPC分类号： H01L21/311 ,  H01L23/58

    CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0337

    摘要： Methods for manufacturing a semiconductor device are provided. In one embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and has a first set of interconnect features. The first film stack comprises a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer. The first photoresist layer is patterned by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.

    摘要翻译： 提供了制造半导体器件的方法。 在一个实施例中，一种方法包括提供具有沉积在其上的第一膜堆叠的基底材料，其中基底材料形成在衬底上并且具有第一组互连特征。 第一薄膜叠层包括沉积在基材表面上的第一非晶碳层，沉积在第一非晶碳层上的第一抗反射涂层和沉积在第一抗反射涂层上的第一光致抗蚀剂层。 通过在第一光致抗蚀剂层上相对于衬底的掩模的投影横向移动所需的距离来对第一光致抗蚀剂层进行构图，从而将第一特征图案引入第一光刻胶层以转移到下面的基底材料，其中第一 特征图案不与第一组互连特征对齐。

    CABLE SYSTEM WITH SELECTIVE DEVICE ACTIVATION FOR A VEHICLE
    6.
    发明申请
    CABLE SYSTEM WITH SELECTIVE DEVICE ACTIVATION FOR A VEHICLE 审中-公开
    具有用于车辆的选择性设备激活的电缆系统

    公开(公告)号：US20120033746A1

    公开(公告)日：2012-02-09

    申请号：US13265371

    申请日：2010-04-22

    申请人： Patrick Reilly

    发明人： Patrick Reilly

    IPC分类号： H04B3/00

    CPC分类号： H04L12/12 ,  B60R16/023 ,  B60R16/03 ,  H04L12/40013 ,  Y02D50/40

    摘要： The present invention relates to a cable system (100) for a vehicle, the cable system (100) being suitable for providing an operative link between a plurality of devices (110) in the vehicle and their associated activation (112), which associated activation switches (112) are spaced apart from the devices (110), the cable system (100) comprising a wiring loom (108) comprising a single signal wire (204); for each device, a receiver assembly (104) connectable to the device and a transmitter assembly (102) connectable to the device's associated activation switch, wherein the clock pulses and signal pulses are of substantially equal amplitude. The invention further relates to a method on controlling devices within a vehicle and transmitter and received assemblies. The invention provides a convenient, efficient and cost-effective manner of controlling devices within a vehicle.

    摘要翻译： 本发明涉及一种用于车辆的电缆系统（100），所述电缆系统（100）适用于在车辆中的多个设备（110）及其相关联的激活（112）之间提供可操作的连接，所述激活 开关（112）与设备（110）间隔开，电缆系统（100）包括包括单个信号线（204）的布线织机（108）; 对于每个设备，可连接到所述设备的接收器组件（104）和可连接到所述设备的相关联的激活开关的发射器组件（102），其中所述时钟脉冲和信号脉冲具有基本相等的振幅。 本发明还涉及一种用于控制车辆和发射器和接收组件内的装置的方法。 本发明提供了一种方便，高效和成本有效的方式来控制车辆内的装置。

    PECVD MULTI-STEP PROCESSING WITH CONTINUOUS PLASMA
    7.
    发明申请
    PECVD MULTI-STEP PROCESSING WITH CONTINUOUS PLASMA 审中-公开
    PECVD多步加工连续等离子体

    公开(公告)号：US20110151142A1

    公开(公告)日：2011-06-23

    申请号：US12969333

    申请日：2010-12-15

    申请人： Martin Jay Seamons ,  Sum-Yee Betty Tang ,  Michael H. Lin ,  Patrick Reilly ,  Sudha Rathi

    发明人： Martin Jay Seamons ,  Sum-Yee Betty Tang ,  Michael H. Lin ,  Patrick Reilly ,  Sudha Rathi

    IPC分类号： H05H1/24

    CPC分类号： C23C16/45523 ,  C23C16/4401

    摘要： Embodiments of the present invention provide methods for reducing defects during multi-layer deposition. In one embodiment, the method includes exposing the substrate to a first gas mixture and an inert gas in the presence of a plasma to deposit a first material layer on the substrate, terminating the first gas mixture when a desired thickness of the first material is achieved while still maintaining the plasma and flowing the inert gas, and exposing the substrate to the inert gas and a second gas mixture that are compatible with the first gas mixture in the presence of the plasma to deposit a second material layer over the first material layer in the same processing chamber, wherein the first material layer and the second material layer are different from each other.

    摘要翻译： 本发明的实施例提供了在多层沉积期间减少缺陷的方法。 在一个实施例中，该方法包括在存在等离子体的情况下将衬底暴露于第一气体混合物和惰性气体，以在衬底上沉积第一材料层，当达到所需的第一材料厚度时终止第一气体混合物 同时仍保持等离子体并使惰性气体流动，并将衬底暴露于惰性气体和在存在等离子体的情况下与第一气体混合物相容的第二气体混合物以在第一材料层上沉积第二材料层 相同的处理室，其中第一材料层和第二材料层彼此不同。

    PLANARIZING ETCH HARDMASK TO INCREASE PATTERN DENSITY AND ASPECT RATIO
    8.
    发明申请
    PLANARIZING ETCH HARDMASK TO INCREASE PATTERN DENSITY AND ASPECT RATIO 失效

    公开(公告)号：US20110291243A1

    公开(公告)日：2011-12-01

    申请号：US12790203

    申请日：2010-05-28

    申请人： Martin Jay Seamons ,  Kwangduk Douglas Lee ,  Chiu Chan ,  Patrick Reilly ,  Sudha Rathi

    发明人： Martin Jay Seamons ,  Kwangduk Douglas Lee ,  Chiu Chan ,  Patrick Reilly ,  Sudha Rathi

    IPC分类号： H01L21/302 ,  H01L23/52 ,  G03F7/20 ,  H01L21/30

    CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0337

    摘要： Methods for manufacturing a semiconductor device in a processing chamber are provided. In one embodiment, a method includes depositing over a substrate a first base material having a first set of interconnect features, filling an upper portion of the first set of interconnect features with an ashable material to an extent capable of protecting the first set of interconnect features from subsequent processes while being easily removable when desired, planarizing an upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material, providing a substantial planar outer surface of the first base material, depositing a first film stack comprising a second base material on the substantial planar outer surface of the first base material, forming a second set of interconnect features in the second base material, wherein the second set of interconnect features are aligned with the first set of interconnect features, and removing the ashable material from the first base material, thereby extending a feature depth of the semiconductor device by connecting the second set of interconnect features to the first set of interconnect features. In another embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and having a first set of interconnect features filled with an amorphous carbon material, the first film stack comprising a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer, and patterning a portion of the first photoresist layer by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.