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    Hierarchical global clock tree
    7.
    发明授权
    Hierarchical global clock tree 有权
    分层全局时钟树

    公开(公告)号：US08638138B2

    公开(公告)日：2014-01-28

    申请号：US12559040

    申请日：2009-09-14

    申请人： Ravi Sunkavalli ,  Rahul Nimaiyar ,  Ravi Kurlagunda ,  Vijay Bantval

    发明人： Ravi Sunkavalli ,  Rahul Nimaiyar ,  Ravi Kurlagunda ,  Vijay Bantval

    IPC分类号： H03L7/06

    CPC分类号： G06F1/06 ,  G06F1/10

    摘要： Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

    摘要翻译： 描述了用于形成和操作全局分层时钟树的方法，系统和电路。 全局分层时钟树可以包括时钟电路，其操作以向由时钟电路包围的核心电路提供时钟信号。 时钟电路可以包括分别产生第一和第二组时钟信号的两个或更多个第一和第二时钟发生器模块。 第一和第二时钟模块可以被定位成使得第一组时钟信号经历大致相等的第一延迟，并且第二组时钟信号经历大致相等的第二延迟。 公开了附加的方法，系统和电路。

    Dedicated logic cells employing configurable logic and dedicated logic functions
    9.
    发明授权
    Dedicated logic cells employing configurable logic and dedicated logic functions 有权
    采用可配置逻辑和专用逻辑功能的专用逻辑单元

    公开(公告)号：US07358765B2

    公开(公告)日：2008-04-15

    申请号：US11066336

    申请日：2005-02-23

    申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

    发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728

    摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

    摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

    Programmable logic cells with Local Connections
    10.
    发明申请
    Programmable logic cells with Local Connections 有权
    具有本地连接的可编程逻辑单元

    公开(公告)号：US20060164120A1

    公开(公告)日：2006-07-27

    申请号：US11044386

    申请日：2005-01-27

    申请人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

    发明人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

    摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。