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公开(公告)号：US08298936B1
公开(公告)日：2012-10-30
申请号：US12699738
申请日：2010-02-03
IPC分类号： H01L21/283 , H01L21/67
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/5826 , C23C14/584 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873
摘要： Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.
摘要翻译： 通过涉及至少三个操作的方法将金属种子层沉积在具有凹陷特征的半导体衬底上。 在该方法中，第一金属层沉积在基底上以至少覆盖凹陷特征的底部。 随后重新分布第一金属层以改善凹陷特征的侧壁覆盖。 接下来，在衬底的至少场区域和凹陷特征的底部上沉积第二层金属。 该方法可以使用允许沉积和重新溅射操作的PVD装置来实现。 这种操作顺序可以提供具有改进的台阶覆盖率的种子层。 它还导致互连中空隙的形成减少，并改善形成的IC器件的电阻特性。
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公开(公告)号：US07682966B1
公开(公告)日：2010-03-23
申请号：US11701984
申请日：2007-02-01
申请人： Robert Rozbicki , Bart van Schravendijk , Tom Mountsier , Wen Wu
发明人： Robert Rozbicki , Bart van Schravendijk , Tom Mountsier , Wen Wu
IPC分类号： H01L23/535
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/5826 , C23C14/584 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873
摘要： Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.
摘要翻译： 通过涉及至少三个操作的方法将金属种子层沉积在具有凹陷特征的半导体衬底上。 在该方法中，第一金属层沉积在基底上以至少覆盖凹陷特征的底部。 随后重新分布第一金属层以改善凹陷特征的侧壁覆盖。 接下来，在衬底的至少场区域和凹陷特征的底部上沉积第二层金属。 该方法可以使用允许沉积和重新溅射操作的PVD装置来实现。 这种操作顺序可以提供具有改进的台阶覆盖率的种子层。 它还导致互连中空隙的形成减少，并改善形成的IC器件的电阻特性。
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公开(公告)号：US08592328B2
公开(公告)日：2013-11-26
申请号：US13414619
申请日：2012-03-07
IPC分类号： H01L21/471 , H05H1/24
CPC分类号： C23C16/345 , C23C16/45542 , C23C16/45544 , C23C16/45557 , C23C16/505 , C23C16/52 , C23C16/54 , H01L21/0217 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L29/7843
摘要： Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor.
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公开(公告)号：US08058179B1
公开(公告)日：2011-11-15
申请号：US12343102
申请日：2008-12-23
申请人： Nerissa Draeger , Harald te Nijenhuis , Henner Meinhold , Bart van Schravendijk , Lakshmi Nittala
发明人： Nerissa Draeger , Harald te Nijenhuis , Henner Meinhold , Bart van Schravendijk , Lakshmi Nittala
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02337 , H01L21/76837
摘要： Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the reaction is partially “reset.” A higher overall etch rate is achieved by a multiple exposure with pump down ALR process.
摘要翻译： 实现更高的总体蚀刻速率和原子层去除（ALR）的吞吐量。 反应是一种自限制过程，因此限制了每个循环可蚀刻的材料的总量。 通过在反应操作之间泵送工艺站，反应部分地“重新设置”。通过多次曝光通过泵浦ALR工艺实现更高的总体蚀刻速率。
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5.发明授权Protection of Cu damascene interconnects by formation of a self-aligned buffer layer 有权通过形成自对准缓冲层来保护铜镶嵌互连公开(公告)号：US08030777B1
公开(公告)日：2011-10-04
申请号：US11671161
申请日：2007-02-05
IPC分类号： H01L23/48
CPC分类号： H01L21/76849 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76856 , H01L21/76867 , H01L21/76886
摘要： Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.
摘要翻译： 在制造电子部件的方法和根据这些方法制造的电子部件的过程中保护暴露的金属镶嵌互连表面的方法。 具有暴露的金属表面的镶嵌区域的集成电路结构被提供到封闭处理室中，由此第一反应物与暴露的金属表面接触以将金属层的顶部部分转变成保护性自对准缓冲层。 使第一反应物与该金属层的金属原子反应的分子在该金属层内完全形成保护性自对准缓冲层。 或者，将表面活性反应物分子吸附到暴露的金属表面上形成保护性自对准缓冲层。 可以将第二反应物与保护性自对准缓冲层接触以在保护性自对准缓冲层上直接形成自对准电介质盖层。
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公开(公告)号：US20110151678A1
公开(公告)日：2011-06-23
申请号：US12964110
申请日：2010-12-09
申请人： Kaihan Ashtiani , Michael Wood , John Drewery , Naohiro Shoda , Bart van Schravendijk , Lakshminarayana Nittala , Nerissa Draeger
发明人： Kaihan Ashtiani , Michael Wood , John Drewery , Naohiro Shoda , Bart van Schravendijk , Lakshminarayana Nittala , Nerissa Draeger
IPC分类号： H01L21/31
CPC分类号： H01L21/02274 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02208 , H01L21/76224
摘要： Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.
摘要翻译： 提供了包括沉积可流动氧化物膜和高密度等离子体化学气相沉积氧化物（HDP氧化物）膜的新型间隙填充方案。 根据各种实施方案，可流动的氧化物膜可以用作牺牲层和/或用作自底向上间隙填充的材料。 在某些实施例中，填充间隙的顶表面是HDP氧化物膜。 所得到的填充间隙可以仅用HDP氧化物膜或HDP氧化物和可流动氧化物膜的组合填充。 这些方法提供了改进的顶帽减少并且避免了限定间隙的结构的限制。
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7.发明申请公开(公告)号：US20110117678A1
公开(公告)日：2011-05-19
申请号：US12973549
申请日：2010-12-20
IPC分类号： H01L21/268 , H01L21/306 , B01J19/12
CPC分类号： H01L21/3105 , H01L21/67115 , H01L21/76813 , H01L21/76814 , H01L21/76825
摘要： A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.
摘要翻译： 一种用于含碳低k电介质和相关装置的紫外（UV）处理方法使得能够进行过程诱导的损伤修复。 本发明的方法特别适用于在镶嵌处理中恢复在加工期间损坏的电介质损失的低k特性，预金属化，后平面化或两者。 UV处理可以包括将受试者低k电介质暴露于约束的紫外光谱分布和/或化学甲硅烷基化试剂，或两者。
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公开(公告)号：US07705431B1
公开(公告)日：2010-04-27
申请号：US12060344
申请日：2008-04-01
IPC分类号： H01L21/44
CPC分类号： H01L21/76826 , H01L21/76808 , H01L21/76828 , H01L21/76832 , Y10S438/902
摘要： A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.
摘要翻译： 在半导体器件和集成电路的形成中提高层之间的粘合力的方法以及所得到的中间半导体结构，其包括其上具有低k绝缘层的衬底层。 低k绝缘层包括被吸附的气态颗粒的处理表面积。 该经处理的表面积是通过在加热的低k绝缘层的表面上流动气体，优选硅烷，乙硅烷，二氯硅烷，锗烷或其组合形成的，以将这种气态颗粒吸附到加热表面上，其中绝缘层保持 其原始厚度。 然后将覆盖层直接沉积在绝缘层上，其中绝缘层的经处理的表面区域显着地改善了在形成集成电路的后续处理步骤期间在绝缘层和封盖层之间的粘附。
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9.发明授权Protection of Cu damascene interconnects by formation of a self-aligned buffer layer 有权通过形成自对准缓冲层来保护铜镶嵌互连公开(公告)号：US07396759B1
公开(公告)日：2008-07-08
申请号：US10980076
申请日：2004-11-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76856 , H01L21/76867 , H01L21/76886
摘要： Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.
摘要翻译： 在制造电子部件的方法和根据这些方法制造的电子部件的过程中保护暴露的金属镶嵌互连表面的方法。 具有暴露的金属表面的镶嵌区域的集成电路结构被提供到封闭处理室中，由此第一反应物与暴露的金属表面接触以将金属层的顶部部分转变成保护性自对准缓冲层。 使第一反应物与该金属层的金属原子反应的分子在该金属层内完全形成保护性自对准缓冲层。 或者，将表面活性反应物分子吸附到暴露的金属表面上形成保护性自对准缓冲层。 可以将第二反应物与保护性自对准缓冲层接触以在保护性自对准缓冲层上直接形成自对准电介质盖层。
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公开(公告)号：US06787483B1
公开(公告)日：2004-09-07
申请号：US10442846
申请日：2003-05-20
申请人： Atiye Bayman , Md Sazzadur Rahman , Weijie Zhang , Bart van Schravendijk , Vishal Gauri , George D. Papasoulitotis , Vikram Singh
发明人： Atiye Bayman , Md Sazzadur Rahman , Weijie Zhang , Bart van Schravendijk , Vishal Gauri , George D. Papasoulitotis , Vikram Singh
IPC分类号： H01L2131
CPC分类号： H01L21/02129 , C23C16/045 , C23C16/402 , H01J2237/3327 , H01L21/02131 , H01L21/0214 , H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/76224
摘要： Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.
摘要翻译： 使用化学气相沉积方法来填充高纵横比（通常至少3:1），窄宽度（通常为1.5微米或更小甚至0.15微米以下）间隙，空隙或弱点的发生率显着降低。 该沉积工艺涉及在含等离子体CVD反应器的反应混合物中使用氢作为工艺气体。 工艺气体还包括电介质形成前体分子，例如硅和含氧分子。
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