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公开(公告)号：US5939945A
公开(公告)日：1999-08-17
申请号：US900345
申请日：1997-07-25
摘要： Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.
摘要翻译： 提供了具有至少一个神经元MOS晶体管的放大器电路，其中耦合栅极连接到放大器输出和至少一个另外的耦合栅极与相应的放大器输入连接。 放大器电路即使在大信号操作中也表现出线性传输行为，并且可以使用相对较少的部件来构造。 此外，增益容易设定。
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2.发明授权Devices for the self-adjusting setting of the operating point in amplifier circuits with neuron MOS transistors 失效用于具有神经元MOS晶体管的放大器电路中的工作点的自调整设置的装置
公开(公告)号：US5942912A
公开(公告)日：1999-08-24
申请号：US900119
申请日：1997-07-25
摘要： A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.
摘要翻译： 依赖于可设定的零点电压目标值（V0，sol1）的定义零点电压（V0）在具有神经元MOS晶体管（T10,1 ... T10，k）的放大器级（1 ... k）中被使能 ）。 这通常是因为，例如，由于神经元MOS晶体管的浮置栅极的处理引起的充电，并且由于来自沟道区的电容耦合电压，传输特性曲线的未定义的零点位移 结果。 这些器件可以与放大器级一起使用，例如， 视频和音频技术，传感器技术，模拟电脑，模糊电路和神经网络。
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3.发明授权Digital/analog converter using a floating gate MOS neuron transistor with capacitive coupling 失效数字/模拟转换器采用具有电容耦合的浮栅MOS神经元晶体管
公开(公告)号：US6037885A
公开(公告)日：2000-03-14
申请号：US7252
申请日：1998-01-14
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03M1/66 , H03M1/74 , H03M1/80 , H03M1/00
CPC分类号： H03M1/802
摘要： A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.
摘要翻译： 数字/模拟转换器具有神经元MOS晶体管，保持神经元MOS晶体管的漏极电位恒定的维护电路和电流源。 在大信号方面的线性动态范围是可能的，因此具有比例如仅两位更大的输入字大小的转换器可以以低耗散功率以简单的方式实现。 这种转换器对于ULSI电路尤其重要。
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4.发明授权
公开(公告)号：US6097661A
公开(公告)日：2000-08-01
申请号：US161004
申请日：1998-09-25
申请人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
发明人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
CPC分类号： G11C7/1018 , G11C8/04
摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.
摘要翻译： 在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器 端子（Q，+ E，ovs Q + EE）。 两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。 每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。 存储器由时钟信号控制。 这导致有利的表面要求和功率损耗低以及高速度。
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公开(公告)号：US5751742A
公开(公告)日：1998-05-12
申请号：US626512
申请日：1996-04-02
CPC分类号： G11C29/86 , G06F11/1008 , G11C29/88
摘要： In a serially working memory unit with a memory matrix, a row selection unit and a column selection unit are configured such that, given faulty rows or columns, only correctable, single errors or errors of few successive bits occur. This memory unit offers advantages particularly for read-only memories since, due to the memory contents that are already determined during manufacture, substitute rows or columns can thereby not be provided.
摘要翻译： 在具有存储器矩阵的串行工作存储器单元中，行选择单元和列选择单元被配置为使得给定有故障的行或列仅发生少数连续位的可校正的单个错误或错误。 该存储单元特别对于只读存储器提供了优点，因为由于在制造期间已经确定的存储器内容，因此可以不提供代替行或列。
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6.发明授权
公开(公告)号：US5825701A
公开(公告)日：1998-10-20
申请号：US682022
申请日：1996-07-16
IPC分类号： G11C11/412 , G11C7/12 , G11C17/12 , G11C7/00
CPC分类号： G11C7/12 , G11C17/126
摘要： The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).
摘要翻译： 存储单元布置具有连接在位线（4,41）之间并通过选择线（5）逐行连接的MOS晶体管（10）。 为了对所有位线（4,41）进行预充电而不阻塞访问这些线路，连接在位线（4,41）和电源线（7）之间的另外的MOS晶体管（20）被提供， 其栅极端子（202）连接到公共预充电线（6）。
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公开(公告)号：US5831892A
公开(公告)日：1998-11-03
申请号：US904373
申请日：1997-08-01
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C2211/5631 , G11C2211/5634 , G11C7/1006
摘要： A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.
摘要翻译： 具有改进的虚拟地面架构和评估电路的矩阵存储器，可以在读取事件期间在位线上同时读取两个相邻存储器单元的信息内容。 具有信息“0”的存储单元例如由具有低阈值电压的各自的场效应晶体管实现。 为读出提供的每个位线连接到同一行中的两个相邻场效应晶体管的漏极端子。 源端子被施加到彼此不同的两个电位之一。 取决于在选择相关字线时场效应晶体管是导通的，在位线上获得不同的合成电位。 然后将这些电位在评估电路中转换为表示读取信息的二进制信号。
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8.发明授权Device for the jump-like addressing of specific lines of a serially operating digital memory 失效用于串行操作数字存储器的特定线路的跳转寻址的设备
公开(公告)号：US6138227A
公开(公告)日：2000-10-24
申请号：US43046
申请日：1998-03-13
CPC分类号： G11C8/04
摘要： A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.
摘要翻译： PCT No.PCT / DE96 / 01511 Sec。 371日期1998年3月13日 102（e）1998年3月13日PCT PCT 1996年8月13日PCT公布。 公开号WO97 / 10600 日期1997年3月20日具有行和列的存储单元的数字存储器矩阵，存储器单元的寻址由执行地址的任意跳跃的控制设备实现，从而避免在相邻行上寻址。 跳跃增量可选。 控制装置是控制链，其中两个被提供，并且控制链的输出连接到链接元件，连接元件又连接到存储器线。 连接元件分组提供。
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9.发明授权
公开(公告)号：US5825686A
公开(公告)日：1998-10-20
申请号：US875955
申请日：1997-08-11
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L29/792 , G11C11/34
CPC分类号： H01L29/7923 , G11C11/56 , G11C11/5671 , G11C11/5692 , G11C16/0475
摘要： The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.
摘要翻译： PCT No.PCT / DE96 / 00168 Sec。 371日期1997年8月11日 102（e）日期1997年8月11日PCT 1996年2月5日PCT公布。 出版物WO96 / 25741 日期1996年8月22日本发明涉及一种多值只读存储位置，其被对称地构造用于存储第一或第二状态（M，M“'）并且不对称地用于存储至少第三状态（M'，M ''）。 其优点首先是在不显着增加支出的情况下将存储容量加倍，而不损害相对于常规存储位置的信噪比。 本发明适用于电可编程和掩模可编程只读存储器，特别是用于低电压技术的存储器。
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公开(公告)号：US5732013A
公开(公告)日：1998-03-24
申请号：US780494
申请日：1997-01-08
CPC分类号： G11C8/10 , G11C17/126
摘要： A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.
摘要翻译： 具有以行和列排列的存储晶体管的矩阵存储器。 可以通过字线和位线寻址存储晶体管。 控制晶体管通过控制线驱动。 控制晶体管可以短路单元阵列的所有列，即位线，除了要读出的存储单元所在的列之外。
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