公开(公告)号：US20070111466A1

公开(公告)日：2007-05-17

申请号：US11164290

申请日：2005-11-17

申请人： Ronald DellaGuardia ,  Daniel Edelstein ,  Habib Hichri ,  Vincent McGahay

发明人： Ronald DellaGuardia ,  Daniel Edelstein ,  Habib Hichri ,  Vincent McGahay

IPC分类号： H01L21/76

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/31133 ,  H01L21/76808

摘要： Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.

摘要翻译： 公开了减少在去除平坦化层例如交联聚合物期间对超低介电常数（ULK）电介质的损伤的方法。 该方法至少部分地用至少轻度交联的聚合物填充开口，随后是平坦化层。 当除去至多轻度交联的聚合物和平坦化层时，与用于交联聚合物的去除化学物质相比，去除至多轻度交联的聚合物去除比去除平坦化层即交联聚合物更容易，并且不损坏周围的电介质 。

公开(公告)号：US20060024961A1

公开(公告)日：2006-02-02

申请号：US10710706

申请日：2004-07-29

申请人： Matthew Angyal ,  Peter Biolsi ,  Lawrence Clevenger ,  Habib Hichri ,  Bernd Kastenmeier ,  Michael Lane ,  Jeffrey Marino ,  Vincent McGahay ,  Theodorus Standaert

发明人： Matthew Angyal ,  Peter Biolsi ,  Lawrence Clevenger ,  Habib Hichri ,  Bernd Kastenmeier ,  Michael Lane ,  Jeffrey Marino ,  Vincent McGahay ,  Theodorus Standaert

IPC分类号： H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76844

摘要： Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

摘要翻译： 在蚀刻步骤之后密封有机ILD层和金属层的方法。 该方法包括蚀刻穿过ILD层并留下下面的金属层帽的剩余部分，将该装置保持在惰性气体中，并将​​衬垫的至少一部分沉积到开口中以密封ILD层和金属层。 随后的处理可以包括通过蚀刻穿过衬套的一部分和盖层的剩余部分以及沉积金属来形成通孔。

公开(公告)号：US20060190846A1

公开(公告)日：2006-08-24

申请号：US11403332

申请日：2006-04-13

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： G06F17/50

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工过程中支持芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20050118803A1

公开(公告)日：2005-06-02

申请号：US10726140

申请日：2003-12-02

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械的积累。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20060183062A1

公开(公告)日：2006-08-17

申请号：US10906268

申请日：2005-02-11

申请人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： G03F7/00

CPC分类号： G03F7/2022

摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。

公开(公告)号：US20060183315A1

公开(公告)日：2006-08-17

申请号：US10906267

申请日：2005-02-11

申请人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nittta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nittta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be applied before irradiation. The capping material is perforated to allow an etchant to pass therethrough to the substrate below the capping material. The exposed portions of the substrate are removed from underneath the capping material by etching. The capping material is then sealed leaving sealed airgaps within the substrate.

摘要翻译： 提供了一种形成气隙的方法，其中将阻挡掩模施加到基板以将基板的一部分与能量束屏蔽。 照射后，去除阻挡掩模，并将封盖材料施加到基底上。 或者，可以在照射之前施加封盖材料。 封盖材料被穿孔以允许蚀刻剂从其穿过覆盖材料下方的基底。 通过蚀刻从封盖材料的下方去除衬底的暴露部分。 然后密封封盖材料，留下基板内的密封气囊。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20080118717A1

公开(公告)日：2008-05-22

申请号：US12018640

申请日：2008-01-23

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： B32B3/00

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20070158851A1

公开(公告)日：2007-07-12

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US20060027842A1

公开(公告)日：2006-02-09

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L29/76

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.