公开(公告)号：US5807773A

公开(公告)日：1998-09-15

申请号：US688587

申请日：1996-07-30

申请人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

发明人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

IPC分类号： H01L21/04 ,  H01L21/337

CPC分类号： H01L29/66068 ,  Y10S438/931

摘要： A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.

摘要翻译： 一种对准碳化硅静电感应晶体管的栅极和源极的方法，包括以下步骤：在所述晶体管上沉积氧化物层，从所述氧化物层形成氧化物间隔物，其中所述氧化物间隔物邻近所述源，在所述氧化物层上沉积金属层 去除氧化物间隔物，使得所得到的栅极与源极准确对准。

公开(公告)号：US5612547A

公开(公告)日：1997-03-18

申请号：US462405

申请日：1995-06-05

申请人： Rowland C. Clarke ,  Richard R. Siergiej ,  Saptharishi Sriram

发明人： Rowland C. Clarke ,  Richard R. Siergiej ,  Saptharishi Sriram

IPC分类号： H01L29/24 ,  H01L29/772 ,  H01L29/808 ,  H01L29/812 ,  H01L31/0312 ,  H01L27/095 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/1608 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8122

摘要： A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.

摘要翻译： 尽管可以使用任何碳化硅多型体，但由碳化硅制成的静电感应晶体管，优选为6H型。 优选的静态感应晶体管是凹入的肖特基势垒栅型。 因此，提供了碳化硅衬底。 然后，在基板上设置碳化硅漂移层，其中漂移层具有远离衬底延伸的两个间隔开的突起或指状物。 漂移层的每个突起具有设置在其上的碳化硅源区域。 然后沿两个突起之间的漂移层提供栅极材料。 在栅极材料上提供导电栅极触点，并且在每个源极区域上提供导电源极触点。 沿着衬底提供导电漏极接触。 考虑静态感应晶体管的其他栅极类型。 例如，可以采用平面肖特基势垒栅极。 此外，可以使用凹入或平面的MOS栅极，如PN结栅极。

公开(公告)号：US5945701A

公开(公告)日：1999-08-31

申请号：US995080

申请日：1997-12-19

申请人： Richard R. Siergiej ,  Anant K. Agarwal ,  Rowland C. Clarke ,  Charles D. Brandt

发明人： Richard R. Siergiej ,  Anant K. Agarwal ,  Rowland C. Clarke ,  Charles D. Brandt

IPC分类号： H01L29/80 ,  H01L29/12 ,  H01L29/772 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812

CPC分类号： H01L29/7722

摘要： A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.

摘要翻译： 具有源极，漏极和栅极区域的静态感应晶体管。 沟道区域被定义在相邻栅极之间，并且从沟道区域的端部到漏极限定漂移区域。 通道和漂移区具有预定的掺杂浓度，其中沟道区的掺杂浓度大于漂移区的掺杂浓度。

公开(公告)号：US5501173A

公开(公告)日：1996-03-26

申请号：US138564

申请日：1993-10-18

申请人： Albert A. Burk, Jr. ,  Donovan L. Barrett ,  Hudson M. Hobgood ,  Rowland C. Clarke ,  Graeme W. Eldridge ,  Charles D. Brandt

发明人： Albert A. Burk, Jr. ,  Donovan L. Barrett ,  Hudson M. Hobgood ,  Rowland C. Clarke ,  Graeme W. Eldridge ,  Charles D. Brandt

IPC分类号： C30B25/02 ,  C30B25/20 ,  H01L21/205

CPC分类号： H01L21/02378 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262 ,  Y10S148/148 ,  Y10S438/931

摘要： A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.

摘要翻译： 提供了在a轴基板上外延生长a轴α-SiC的方法。 通过在晶体中形成一对平行切口，从SiC晶体形成截面。 这些切口中的每一个平行于晶体的c轴。 由晶体形成的部分具有与晶体的c轴平行的相对的a面表面。 具有烃和硅烷的气体混合物通过该部分的一个面表面。 烃和硅烷在该表面上反应形成SiC的外延层。 优选地，SiC在大约1450℃的温度下生长。

公开(公告)号：US5198695A

公开(公告)日：1993-03-30

申请号：US624783

申请日：1990-12-10

申请人： Maurice H. Hanes ,  Rowland C. Clarke ,  Michael C. Driver

发明人： Maurice H. Hanes ,  Rowland C. Clarke ,  Michael C. Driver

IPC分类号： H01L23/373 ,  H01L23/498

CPC分类号： H01L23/49866 ,  H01L23/3731 ,  H01L23/49827 ,  H01L2924/0002

摘要： A bonded structure is described consisting of a semiconductor wafer, preferably gallium arsenide, soldered to a substrate material. A method for forming the structure is also described. The structure provides mechanical support and thermal conductivity for the wafer, as well as a multitude of connections through the substrate material at predetermined locations on the wafer. The substrate material and the soldering process are selected to minimize the resulting stresses in the wafer. A pattern of pads consisting of a refractory metal covered by a solder material is formed on the substrate to maintain space for excess solder in order to avoid the shorting of the individual connections on the wafer, and to control the size and location of voids in the solder upon solidification.

摘要翻译： 描述了焊接到基底材料的半导体晶片，优选砷化镓的结合结构。 还描述了用于形成结构的方法。 该结构为晶片提供机械支撑和导热性，以及在晶片上的预定位置处通过衬底材料的多个连接。 选择衬底材料和焊接工艺以最小化晶片中产生的应力。 在衬底上形成由焊料材料覆盖的难熔金属组成的衬垫图案，以保持多余焊料的空间，以避免晶片上的各个连接的短路，并且控制空隙的尺寸和位置 焊后固化。

公开(公告)号：US4583107A

公开(公告)日：1986-04-15

申请号：US523819

申请日：1983-08-15

申请人： Rowland C. Clarke

发明人： Rowland C. Clarke

IPC分类号： H01L29/423 ,  H01L29/812 ,  H01L29/80 ,  H01L29/06 ,  H01L29/36 ,  H01L29/48

CPC分类号： H01L29/812 ,  H01L29/42316

摘要： A field effect transistor is described incorporating a semiconductor layer over a layer or substrate of semi-insulating semiconductor material and a gate electrode which periodically passes through the semiconductor layer to the substrate to form a plurality of conducting bars in the semiconductor layer for transistor current and which at pinch-off confines the current interior of each conducting bar. The invention overcomes the problem of leakage current at pinch-off, thus improving the efficiency of the field effect transistor as a power amplifier.

摘要翻译： 描述了一种场效应晶体管，其在半绝缘半导体材料的层或衬底上的半导体层和周期性地通过半导体层到衬底以在晶体管电流的半导体层中形成多个导电棒的栅电极，以及 这在夹断时限制了每个导电棒的当前内部。 本发明克服了夹断漏电流的问题，提高了作为功率放大器的场效应晶体管的效率。

公开(公告)号：US07560322B2

公开(公告)日：2009-07-14

申请号：US11248195

申请日：2005-10-13

申请人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

发明人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

IPC分类号： H01L21/338 ,  H01L21/30

CPC分类号： H01L21/76256 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/735 ,  H01L29/7787

摘要： A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

摘要翻译： 用于大功率半导体器件的衬底布置包括在SiC晶片的表面上沉积有Si层的SiC晶片。 具有Si的第一层，SiO 2的中间层和Si的第三层的SOI结构具有与沉积在SiC晶片上的Si结合的第三层Si，形成整体结构。 除去SOI的第一层和SiO 2的中间层，留下可以制造各种半导体器件的纯的第三层Si。 可以在衬底布置的一部分上去除第三层Si和沉积的Si层，使得可以在SiC晶片上制造一个或多个半导体器件，而其他半导体器件可以容纳在纯的第三层Si上。

公开(公告)号：US20080308838A1

公开(公告)日：2008-12-18

申请号：US11808915

申请日：2007-06-13

申请人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

发明人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

IPC分类号： H01L29/739 ,  H01L21/329 ,  H01L21/8232 ,  H01L29/872 ,  H01L27/098

CPC分类号： H01L27/098 ,  H01L21/8232 ,  H01L27/0727 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/872

摘要： In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

摘要翻译： 在一个实施例中，集成半导体器件包括具有源极的第一垂直结型场效应晶体管（VJFET）和设置在第一VJFET源的每一侧上的栅极和具有源极的第二VJFET晶体管，栅极设置在 第二VJFET源的每一侧。 第一VJFET的至少一个栅极通过沟道与第二VJFET的至少一个栅极分离。 集成半导体器件还包括位于第一和第二VJFET之间的结栅势垒肖特基（JBS）二极管。 JBS二极管包括形成与沟道的整流接触的金属接触和与第一和第二VJFET的至少一个栅极的非整流接触，并且金属接触是JBS二极管的阳极。 第一电连接将第一VJFET的栅极，第二VJFET的栅极和JBS二极管的阳极连接到公共栅电极，并且第二电连接将第一VJFET的源极和第二VJFET的源极连接 到共同的源电极。

公开(公告)号：US07253083B2

公开(公告)日：2007-08-07

申请号：US11154641

申请日：2005-06-17

申请人： Rowland C. Clarke ,  Erica C. Elvey ,  Silai V. Krishnaswamy ,  Jeffrey D. Hartman

发明人： Rowland C. Clarke ,  Erica C. Elvey ,  Silai V. Krishnaswamy ,  Jeffrey D. Hartman

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76256 ,  H01L21/3065 ,  Y10S438/977

摘要： First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding, the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.

摘要翻译： 第一和第二半导体晶片被结合在一起，其中至少一个晶片具有第一层硅，中间氧化物层和第二硅层。 第一硅层最初机械地还原其厚度的大约80％至90％。 剩余的硅层通过等离子体蚀刻进一步减小，其可能留下不均匀的厚度。 通过适当的掩蔽，即使通过第二等离子体蚀刻也可以形成不均匀的厚度。 通过用XeF 2或BrF 3的干蚀刻除去剩余的硅，以暴露中间氧化物层。 在接合之前，半导体晶片可以设置有各种半导体器件，通过通过暴露的中间氧化物层形成的通孔来形成电连接。

公开(公告)号：US07098093B2

公开(公告)日：2006-08-29

申请号：US10938602

申请日：2004-09-13

申请人： Rowland C. Clarke ,  Michael E. Aumer

发明人： Rowland C. Clarke ,  Michael E. Aumer

IPC分类号： H01L21/338

CPC分类号： H01L29/7788 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7789

摘要： A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that of the insulating material of the pillars. Electron flow is confined to a narrow channel at the interface of the two materials. Suitable source, drain and gate contacts are included for HEMT operation.

摘要翻译： HEMT型装置具有垂直于垂直于基板的垂直壁的支柱。 支柱是诸如GaN的绝缘半导体材料。 在柱的侧面上设置有诸如AlGaN的半导体材料的阻挡层，该阻挡层的带隙大于柱的绝缘材料的带隙。 电子流被限制在两个材料界面处的窄通道。 HEMT操作包括适合的源极，漏极和栅极触点。