-
1.发明授权Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法公开(公告)号：US07800933B2
公开(公告)日：2010-09-21
申请号：US11496986
申请日：2006-07-31
CPC分类号： G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/165 , G11C2013/0073 , H01L27/101
摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.
摘要翻译： 包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲 二极管在正向偏置下，而复位脉冲以二极管反向施加。 通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。
-
公开(公告)号：US07474000B2
公开(公告)日：2009-01-06
申请号：US10728451
申请日：2003-12-05
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.
摘要翻译： 本发明提供一种通孔和交错路由级结构。 垂直重叠的通孔连接到在不同高度形成的两个或多个路由级别。 路由级别既被形成在通孔下方形成，也可以形成在通孔下方，并且都形成在半导体衬底晶片之上。 以这种方式，可以形成具有小于第一路由级别或第二路由级别的间距的间距的通孔，从而节省空间。
-
公开(公告)号：US08120068B2
公开(公告)日：2012-02-21
申请号：US12344022
申请日：2008-12-24
申请人： Roy E Scheuerlein , Eliyahou Harari
发明人： Roy E Scheuerlein , Eliyahou Harari
IPC分类号： H01L27/02
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/35 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.
摘要翻译： 公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。 共享支柱结构包括两个非易失性存储元件。 每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。 每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。 每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。 各个存储元件各自包括转向元件和状态改变元件。
-
公开(公告)号：US08050109B2
公开(公告)日：2011-11-01
申请号：US12538492
申请日：2009-08-10
申请人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译： 非易失性存储器核心包括一个或多个存储器空间。 每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。 在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。 在存储器操作期间，存储器块被转换为活动状态和非活动状态。 将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。 这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。
-
公开(公告)号：US08105867B2
公开(公告)日：2012-01-31
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
发明人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
IPC分类号： H01L21/00
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译： 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。
-
公开(公告)号：US07426128B2
公开(公告)日：2008-09-16
申请号：US11179122
申请日：2005-07-11
申请人： Roy E Scheuerlein
发明人： Roy E Scheuerlein
IPC分类号： G11C5/06
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/33 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A rewriteable nonvolatile memory includes a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. The memory cell is formed in an array, such as a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. The thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. A select line extending perpendicular to the data line and the reference line controls the transistor.
摘要翻译： 可重写非易失性存储器包括薄膜晶体管和可切换电阻存储元件。 当经受在第一方向施加的设定电压幅值时，可切换电阻元件降低电阻，并且当经受与第一方向相反的第二方向施加的复位电压幅值时，电阻增加。 存储单元形成为阵列，例如在单个衬底上形成多个存储器级的单片三维存储器阵列。 薄膜晶体管和可切换电阻存储元件电气地布置在平行的数据线和参考线之间。 垂直于数据线延伸的选择线和参考线控制晶体管。
-
公开(公告)号：US08320196B2
公开(公告)日：2012-11-27
申请号：US13233602
申请日：2011-09-15
申请人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译： 非易失性存储器核心包括一个或多个存储器空间。 每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。 在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。 在存储器操作期间，存储器块被转换为活动状态和非活动状态。 将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一存储块之间的电荷共享成为可能。 这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。
-
公开(公告)号：US08693233B2
公开(公告)日：2014-04-08
申请号：US13363252
申请日：2012-01-31
申请人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译： 可重写电阻切换存储单元包括串联的第一和第二电容器。 第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。 第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。 第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。 在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。 在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。
-
9.发明授权公开(公告)号：US08110863B2
公开(公告)日：2012-02-07
申请号：US11143355
申请日：2005-06-01
申请人： Roy E Scheuerlein
发明人： Roy E Scheuerlein
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , B82Y10/00 , G11C16/0475 , H01L21/845 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1211 , H01L29/0649 , H01L29/1037 , H01L29/66833 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/78618 , H01L29/7881 , H01L29/792
摘要： A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.
摘要翻译： 描述每个单元具有两个位的可重写非易失性存储单元。 存储单元优选通过通过通道热电子注入方法将电荷存储在介电电荷存储层中或电隔离的导电纳米晶体中来进行操作。 在优选实施例中，通道区域具有波纹形状，在两个存储区域之间提供额外的隔离。 沟道区域被沉积并且优选地由多晶锗或硅 - 锗形成。 本发明的存储单元可以形成在存储器阵列中; 在优选实施例中，在单个衬底上堆叠形成多个存储器级。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.016 秒)
