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    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240421125A1

    公开(公告)日：2024-12-19

    申请号：US18541649

    申请日：2023-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEUNGDUK BAEK

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

    Abstract: A semiconductor package includes an interposer, a first semiconductor chip on the interposer, a connection structure on the interposer, and a second semiconductor chip on the first semiconductor chip and the connection structure. The first semiconductor chip includes a first input/output circuit. The second semiconductor chip includes a second input/output circuit. The connection structure includes a connection substrate, and a connection through-via penetrating the connection substrate and electrically connecting the second semiconductor chip and the interposer. The first input/output circuit and the second input/output circuit are electrically connected to each other.

    SEMICONDUCTOR DEVICE HAVING PLANARIZED PASSIVATION LAYER AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING PLANARIZED PASSIVATION LAYER AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190244878A1

    公开(公告)日：2019-08-08

    申请号：US16124225

    申请日：2018-09-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG LYONG KIM ,  SEUNGDUK BAEK

    IPC: H01L23/488 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/488 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14

    Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

    SEMICONDUCTOR DEVICE HAVING PLANARIZED PASSIVATION LAYER AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING PLANARIZED PASSIVATION LAYER AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210028092A1

    公开(公告)日：2021-01-28

    申请号：US17071137

    申请日：2020-10-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG LYONG KIM ,  SEUNGDUK BAEK

    IPC: H01L23/488 ,  H01L23/538 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240421129A1

    公开(公告)日：2024-12-19

    申请号：US18403242

    申请日：2024-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEUNGDUK BAEK

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

    Abstract: A semiconductor package include a buffer die, a computing die on the buffer die, a plurality of memory dies vertically stacked on each other to form a memory stack, wherein the memory stack is disposed on the computing die, wherein the buffer die, the computing die, and the memory stack are vertically stacked on each other, and wherein the computing die is disposed in a space between the buffer die and the memory stack, and a mold layer covering the computing die and the plurality of memory dies. The buffer die comprises a plurality of outer connection members. The computing die comprises a plurality of computing blocks. Each of the plurality of memory dies comprises a plurality of memory blocks. The plurality of computing blocks are configured to process data received from the plurality of memory blocks and to store the processed results in the plurality of memory blocks.

    SEMICONDUCTOR PACKAGE
    8.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240096717A1

    公开(公告)日：2024-03-21

    申请号：US18213386

    申请日：2023-06-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： AE-NEE JANG ,  SEUNGDUK BAEK

    IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

    CPC classification number: H01L22/32 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/08113 ,  H01L2224/08148 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1435

    Abstract: A semiconductor package includes a first semiconductor chip on a substrate and including a first semiconductor substrate and a first test pattern on a first surface of the first semiconductor substrate, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate and a second test pattern on a second surface of the second semiconductor substrate. The first and second semiconductor chips bonded to allow the first test pattern to face the second test pattern. The first test pattern includes a first in-pad, first connection pads, and a first out-pad. The second test pattern includes a second in-pad bonded to the first in-pad, a second out-pad bonded to the first out-pad, and second connection pads bonded to the first connection pads. The first and second connection pads are connected in series to alternately connect with each other and form a series wiring pattern, so that each first connection pad connects to another first connection pad in one direction along the series wiring pattern and to a second connection pad in an opposite direction along the series wiring pattern.

    SEMICONDUCTOR PACKAGE
    10.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220302087A1

    公开(公告)日：2022-09-22

    申请号：US17509610

    申请日：2021-10-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DONGJOO CHOI ,  SEUNGDUK BAEK

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/367

    Abstract: A semiconductor package includes second semiconductor chip stacked on the first semiconductor chip, a chip adhesive layer between the first and second semiconductor chips, a quadrangular signal pillar and a quadrangular center dummy pillar between a central portion of the second semiconductor chip and the first semiconductor chip, an elliptical corner dummy pillar between a corner portion of the second semiconductor chip and the first semiconductor chip, a signal bump between the signal pillar and the first semiconductor chip, a center dummy bump between the center dummy pillar and the first semiconductor chip and a corner dummy bump section between the corner dummy pillar and the first semiconductor chip. The signal pillar and the signal bump provide an electrical path between the second semiconductor chip and the first semiconductor chip, the center dummy pillar and the center dummy bump provide one thermal path between the second semiconductor chip and the first semiconductor chip, and the corner dummy pillar and the corner dummy bump provide another thermal path between the second semiconductor chip and the first semiconductor chip.

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