公开(公告)号：US09947395B2

公开(公告)日：2018-04-17

申请号：US15486512

申请日：2017-04-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US20170221556A1

公开(公告)日：2017-08-03

申请号：US15486512

申请日：2017-04-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US20170169867A1

公开(公告)日：2017-06-15

申请号：US15151617

申请日：2016-05-11

Applicant: SanDisk Technologies, LLC

Inventor： Amul DESAI ,  Hao Nguyen ,  Man Mui ,  Ohwon Kwon

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/10 ,  H01L27/02

CPC classification number: G11C7/12 ,  G05F1/463 ,  G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/22 ,  H01L27/0211

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

公开(公告)号：US09595338B2

公开(公告)日：2017-03-14

申请号：US14495283

申请日：2014-09-24

Applicant: SanDisk Technologies LLC

Inventor： Juan Carlos Lee ,  Hao Nguyen ,  Man Mui ,  Tien-chien Kuo ,  Yuki Mizutani

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C16/24 ,  G11C7/12 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26

Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Abstract translation: 在NAND闪存中，位线预充/放电时间可以是确定程序，擦除和读取性能的主要组成部分。 在常规布置中，位线电平由感测放大器设置，位线通过读出放大器路径被放电到源极线电平。 在这种布置下，基于位线的RC常数，预充电/放电时间由远端（相对于感测放大器）支配。 因此，减少位线预充电/放电时间，从而提高了NAND​​闪存的性能，从而提高了整体系统的性能。 为了解决这个问题，通过使用虚拟NAND串将额外的路径引入到公共源级别的位线之间。 在基于示例性的基于3D-NAND（BiCS）的实施例中，虚拟NAND串从虚拟块中获取，其中虚拟块可以被放置在整个阵列中以均匀分布放电电流。

公开(公告)号：US09947407B2

公开(公告)日：2018-04-17

申请号：US15599850

申请日：2017-05-19

Applicant: SanDisk Technologies LLC

Inventor： Hao Nguyen ,  Man Mui ,  Khanh Nguyen ,  Seungpil Lee ,  Toru Ishigaki ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/20 ,  G11C13/00

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2213/75 ,  H01L27/11556 ,  H01L27/11582

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

公开(公告)号：US09627046B2

公开(公告)日：2017-04-18

申请号：US14635918

申请日：2015-03-02

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/34 ,  G11C7/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US09959915B2

公开(公告)日：2018-05-01

申请号：US15151617

申请日：2016-05-11

Applicant: SanDisk Technologies LLC

Inventor： Amul Desai ,  Hao Nguyen ,  Man Mui ,  Ohwon Kwon

IPC: G11C7/00 ,  G11C7/12 ,  H01L27/02 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/12 ,  G05F1/463 ,  G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/22 ,  H01L27/0211

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

公开(公告)号：US09633742B2

公开(公告)日：2017-04-25

申请号：US14328018

申请日：2014-07-10

Applicant: SanDisk Technologies LLC

Inventor： Amul Dhirajbhai Desai ,  Hao Nguyen ,  Seungpil Lee ,  Man Mui

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/34 ,  G11C7/08 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/16

CPC classification number: G11C16/32 ,  G11C7/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/11582

Abstract: In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

公开(公告)号：US20170256317A1

公开(公告)日：2017-09-07

申请号：US15599850

申请日：2017-05-19

Applicant: SanDisk Technologies LLC

Inventor： Hao Nguyen ,  Man Mui ,  Khanh Nguyen ,  Seungpil Lee ,  Toru Ishigaki ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2213/75 ,  H01L27/11556 ,  H01L27/11582

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

公开(公告)号：US09659656B2

公开(公告)日：2017-05-23

申请号：US15062987

申请日：2016-03-07

Applicant: SanDisk Technologies LLC

Inventor： Hao Nguyen ,  Man Mui ,  Khanh Nguyen ,  Seungpil Lee ,  Toru Ishigaki ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582 ,  G11C13/00

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2213/75 ,  H01L27/11556 ,  H01L27/11582

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.