公开(公告)号：US09208827B2

公开(公告)日：2015-12-08

申请号：US14526802

申请日：2014-10-29

Applicant: SK hynix Inc.

Inventor： Ki Yong Lee ,  Jong Hyun Kim ,  Sang Hwan Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  G11C5/02 ,  H01L25/065 ,  H01L23/00 ,  G11C7/14 ,  H01L23/525 ,  G11C7/10 ,  G11C5/14 ,  G11C29/12

CPC classification number: G11C5/025 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14 ,  G11C7/20 ,  G11C29/1201 ,  G11C2207/105 ,  H01L23/5256 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0901 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Abstract translation: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底，堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元，并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元，设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。

公开(公告)号：US11482261B2

公开(公告)日：2022-10-25

申请号：US17242988

申请日：2021-04-28

Applicant: SK hynix Inc.

Inventor： Sang Hwan Kim

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

公开(公告)号：US10902898B2

公开(公告)日：2021-01-26

申请号：US16503739

申请日：2019-07-05

Applicant: SK hynix Inc.

Inventor： Sang Hwan Kim

IPC: G11C8/10 ,  G11C8/18 ,  G11C8/06 ,  G06F12/02 ,  G11C7/12 ,  G11C7/22 ,  G06F12/0888 ,  G11C29/44

Abstract: A semiconductor memory device includes a memory cell array, a buffer unit, control logic, and a decoding circuit. The memory cell array includes a plurality of memory cells. The buffer coupled to the memory cell array, and includes a first memory area, a second memory area, and a conversion memory area. The control logic outputs a mode control signal representing an operating mode of the buffer. The decoding circuit controls the operating mode of the buffer such that the conversion memory area operates as any one of a main memory area and a repair memory area, based on the mode control signal.

公开(公告)号：US10796769B2

公开(公告)日：2020-10-06

申请号：US16299590

申请日：2019-03-12

Applicant: SK hynix Inc.

Inventor： Sang Hwan Kim ,  Min Su Kim ,  Kyeong Min Chae

IPC: G06F3/06 ,  G11C16/24 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11556

Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

公开(公告)号：US10002851B2

公开(公告)日：2018-06-19

申请号：US15248435

申请日：2016-08-26

Applicant: SK hynix Inc.

Inventor： Ki Yong Lee ,  Sang Hwan Kim ,  Hyung Ju Choi

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/105 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/105 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

公开(公告)号：US09665118B2

公开(公告)日：2017-05-30

申请号：US15045494

申请日：2016-02-17

Applicant: SK hynix Inc.

Inventor： Sang Hwan Kim

IPC: G05F5/00

CPC classification number: G05F5/00

Abstract: A semiconductor apparatus includes a controller configured to generate a plurality of control signals for selecting an operation mode of the semiconductor apparatus in response to a number of input chip enable pulses, and an output driving unit configured to be operated according to the operation mode of the semiconductor apparatus based on the plurality of control signals.

公开(公告)号：US11373722B2

公开(公告)日：2022-06-28

申请号：US17149495

申请日：2021-01-14

Applicant: SK hynix Inc.

Inventor： Sang Hwan Kim

IPC: G11C29/12 ,  G11C29/38 ,  G11C29/14 ,  G11C16/04

Abstract: A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.