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    Delaying Hot Block Garbage Collection with Adaptation
    1.
    发明申请
    Delaying Hot Block Garbage Collection with Adaptation 审中-公开
    延迟热块垃圾收集与适应

    公开(公告)号：US20170060428A1

    公开(公告)日：2017-03-02

    申请号：US15253123

    申请日：2016-08-31

    Applicant: SK Hynix Memory Solutions Inc.

    Inventor： Frederick K.H. Lee ,  Xiangyu Tang ,  Lingqi Zeng

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0652 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0688 ,  G06F13/16 ,  G11C16/10

    Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

    Abstract translation: 存储器系统可以包括存储器存储器和适于测量第一当前窗口的写入放大（WA）值的控制器，将第一窗口的WA值与先前窗口的先前WA值进行比较，以及计算和设置 基于当前窗口阈值的WA值与先前窗口阈值的WA值的比较来确定比率阈值的值。

    SOFT INPUT, SOFT OUPUT MAPPERS AND DEMAPPERS FOR BLOCK CODES
    4.
    发明申请
    SOFT INPUT, SOFT OUPUT MAPPERS AND DEMAPPERS FOR BLOCK CODES 审中-公开
    软输入，软件映射器和块代码的代码

    公开(公告)号：US20140189458A1

    公开(公告)日：2014-07-03

    申请号：US14146929

    申请日：2014-01-03

    Applicant: SK hynix memory solutions inc.

    Inventor： Frederick K.H. Lee ,  Jason Bellorado ,  Zheng Wu ,  Marcus Marrow

    IPC: H03M13/11

    CPC classification number: H03M13/1111 ,  G11B2020/185 ,  G11B2220/2508 ,  H03M13/612 ,  H03M13/6325 ,  H03M13/6343 ,  H04L1/0054 ,  H04L1/0057

    Abstract: A codebook which includes a plurality of messages and a plurality of codewords, a specified codeword bit value, and a specified message bit value are obtained. The LLR for bit ci in a codeword is generated, including by: identifying, from the codebook, those codewords where bit ci has the specified codeword bit value; for a message which corresponds to one of the codewords where bit ci has the specified codeword bit value, identifying those bits which have the specified message bit value; and summing one or more LLR values which correspond to those bits, in the message which corresponds to one of the codewords where bit ci has the specified codeword bit value, which have the specified message bit value.

    Abstract translation: 获得包括多个消息和多个码字的码本，指定的码字比特值和指定的消息比特值。 产生码字中的比特ci的LLR，包括：从码本中识别比特ci具有指定码字比特值的那些码字; 对于与其中位ci具有指定码字比特值的码字之一相对应的消息，识别具有指定消息比特值的那些比特; 并且在对应于具有指定消息比特值的比特ci具有指定码字比特值的码字中的一个的消息中对与这些比特相对应的一个或多个LLR值求和。

    POWER SAVING TECHNIQUES THAT USE A LOWER BOUND ON BIT ERRORS
    6.
    发明申请
    POWER SAVING TECHNIQUES THAT USE A LOWER BOUND ON BIT ERRORS 有权
    在BIT错误上使用较低限制的节电技术

    公开(公告)号：US20140013166A1

    公开(公告)日：2014-01-09

    申请号：US13902410

    申请日：2013-05-24

    Applicant: SK HYNIX MEMORY SOLUTIONS INC.

    Inventor： Arunkumar Subramanian ,  Frederick K.H. Lee ,  Jason Bellorado ,  Xiangyu Tang ,  Lingqi Zeng

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/32 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G11C7/00 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.

    Abstract translation: 获得回读比特序列和电荷约束信息。 至少部分地基于回读比特序列和电荷约束信息来确定与回读比特序列相关联的多个比特错误的下限。 比较与纠错解码器相关联的下限和纠错能力阈值。 在下限大于或等于纠错能力阈值的情况下，预测出纠错解码失败，并且响应于该预测，将部件配置为节省功率。

    FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY
    7.
    发明申请
    FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY 审中-公开
    找到最佳读取阈值和固态存储器的相关电压

    公开(公告)号：US20150138894A1

    公开(公告)日：2015-05-21

    申请号：US14546545

    申请日：2014-11-18

    Applicant: SK hynix memory solutions inc.

    Inventor： Xiangyu Tang ,  Lingqi Zeng ,  Jason Bellorado ,  Frederick K.H. Lee ,  Arunkumar Subramanian

    IPC: G11C16/26

    CPC classification number: G11C16/26

    Abstract: A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics.

    Abstract translation: 使用被设置为默认电压的读取阈值电压的第一次迭代来执行读取以获得第一特性。 使用默认电压和偏移量产生读取阈值电压的第二次迭代。 使用读取阈值电压的第二次迭代执行读取以获得第二特性。 使用第一和第二特性产生读取阈值电压的第三次迭代。 使用读取阈值电压的第三次迭代执行读取以获得第三特性。 确定第三特性是否是最接近存储特性的两个特征之一。 如果是这样，则使用两个最接近的特性来产生读取阈值电压的第四次迭代。

    THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS
    8.
    发明申请
    THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS 有权
    使用位数计数和最小值的阈值估计

    公开(公告)号：US20150131376A1

    公开(公告)日：2015-05-14

    申请号：US14480988

    申请日：2014-09-09

    Applicant: SK hynix memory solutions inc.

    Inventor： Christopher S. Tsang ,  Frederick K.H. Lee ,  Xiangyu Tang ,  Zheng Wu ,  Jason Bellorado

    IPC: G11C16/34 ,  G11C16/26

    CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C16/3404

    Abstract: A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold.

    Abstract translation: 包括通过以下步骤确定每个仓的位翻转计数：（1）在对应于给定仓的下限的第一阈值处对一组固态存储单元执行第一次读取，并且（2 ）在对应于给定仓的上限的第二阈值对所述固态存储单元组执行第二读取。 使用与多个箱相对应的位翻转计数来确定最小值，并且使用最小值来估计最佳阈值。

    GENERATING READ THRESHOLDS USING GRADIENT DESCENT AND WITHOUT SIDE INFORMATION
    9.
    发明申请
    GENERATING READ THRESHOLDS USING GRADIENT DESCENT AND WITHOUT SIDE INFORMATION 审中-公开
    生成使用梯级下载并且无信息的读取阈值

    公开(公告)号：US20150078084A1

    公开(公告)日：2015-03-19

    申请号：US14550764

    申请日：2014-11-21

    Applicant: SK hynix memory solutions inc.

    Inventor： Frederick K.H. Lee ,  Jason Bellorado ,  Arunkumar Subramanian ,  Lingqi Zeng ,  Xiangyu Tang ,  Ameen Aslam

    IPC: G11C16/26 ,  G11C16/10

    CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/3404

    Abstract: A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read.

    Abstract translation: 读取固态存储器中的单元的第一位位置，其中使用第一位位置的读取获得排序位。 第一次读取单元的第二位位置，包括通过将与第二位位置相关联的第一读取阈值设置为第一值并将与第二位位置相关联的第二读取阈值设置为第二值。 第二次读取单元的第二位位置，包括通过将第一读取阈值设置为第三值并将第二读取阈值设置为第四值。 使用排序位，第一读取和第二读取生成第一读取阈值和第二读取阈值的新值。

    STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION
    10.
    发明申请
    STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION 审中-公开
    存储使用线性近似的NAND闪存存储读取阈值

    公开(公告)号：US20150085572A1

    公开(公告)日：2015-03-26

    申请号：US14553745

    申请日：2014-11-25

    Applicant: SK hynix memory solutions inc.

    Inventor： Arunkumar Subramanian ,  Xiangyu Tang ,  Jason Bellorado ,  Lingqi Zeng ,  Frederick K.H. Lee

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

    Abstract: A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block.

    Abstract translation: 接收与块中的第一页相关联的第一读取阈值和与块中的第二页相关联的第二读取阈值，其中第一页面具有第一页面编号，并且第二页面具有第二页面编号。 至少部分地基于第一读取阈值，第二读取阈值，第一页面编号和第二页面数量来确定斜率和y截距。 斜率和y截距用与块相关联的块标识符存储。

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