公开(公告)号：US20190319157A1

公开(公告)日：2019-10-17

申请号：US16378153

申请日：2019-04-08

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Pte Ltd

Inventor： Romain COFFY ,  Laurent HERARD ,  David GANI

IPC: H01L31/12 ,  H01L31/0203

Abstract: A carrier wafer has a back face and a front face and a network of electrical connections between the back face and the front face. A first electronic chip is mounted with its bottom face on top of the front face of the carrier wafer. The first electronic chip has a through-opening extending between the bottom face and a face. A second electronic chip is installed in the through-opening and mounted to the front face of the carrier wafer.

公开(公告)号：US20140191387A1

公开(公告)日：2014-07-10

申请号：US14177146

申请日：2014-02-10

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Grenoble 2 SAS

Inventor： Yonggang JIN ,  Romain COFFY ,  Jerome TEYSSEYRE

IPC: H01L23/498 ,  H01L23/34

CPC classification number: H01L23/498 ,  H01L21/561 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/49124 ,  Y10T29/49174 ,  Y10T29/49204 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract translation: 扇出晶片级封装设置有嵌入重构晶片中的半导体管芯。 再分配层位于半导体管芯上方，并且在封装的表面上包括焊盘栅格阵列。 铜管散热器形成在芯片上的再分配层中，与多个配置成将半导体管芯的电路焊盘耦合到焊盘栅极阵列的接触焊盘的多个电迹线相同的层中。 在操作中，散热器提高了从模具到电路板的热传递的效率。

公开(公告)号：US20240168245A1

公开(公告)日：2024-05-23

申请号：US18389377

申请日：2023-11-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Younes BOUTALEB

IPC: G02B6/42

CPC classification number: G02B6/4257 ,  G02B6/4238 ,  G02B6/4239 ,  G02B6/4245 ,  G02B6/4274

Abstract: An integrated circuit package includes an assembly of an electronic integrated circuit chip, an optical element and a support substrate. The support substrate includes a mounting face and has an opening sized and shaped to containing the electronic integrated circuit chip. The optical element includes a connection face connected to the mounting face of the support substrate and is positioned opposite to said opening. The electronic integrated circuit chip is connected to the connection face of the optical element such that the electronic chip is housed in said opening of the support substrate.

公开(公告)号：US20230140705A1

公开(公告)日：2023-05-04

申请号：US17970327

申请日：2022-10-20

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Younes BOUTALEB ,  Romain COFFY

IPC: H01L23/367 ,  H01L21/52 ,  H01L23/498

Abstract: The present description concerns an electronic device comprising an electronic chip and a package for protecting said chip, said package comprising: a substrate comprising an alternation of electrically-insulating layers and of thermally-conductive layers where at least one electrically-insulating layer comprises at least a thermally-conductive portion; and a cover made of a thermally-conductive material comprising at least one lateral portion arranged in at least one cavity formed from a first surface of said substrate.

公开(公告)号：US20190376676A1

公开(公告)日：2019-12-12

申请号：US16439308

申请日：2019-06-12

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Joseph HANNAN ,  Stuart ROBERTSON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: F21V23/04 ,  H05B33/08 ,  F21V23/00 ,  H01L33/44 ,  H01L23/00 ,  F21K9/20

Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a molded body having an opening permitting the passage of a light beam generated by the light source; one or more surfaces for receiving a diffuser; and first and second conducting pins traversing the molded body, each pin abutting one of said surfaces.

公开(公告)号：US20190356390A1

公开(公告)日：2019-11-21

申请号：US16409723

申请日：2019-05-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre COULLOMB ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H04B10/40 ,  H04B10/50 ,  H04B10/69 ,  H01L31/0203 ,  H01L25/04

Abstract: An optoelectronic device includes a substrate and a first optoelectronic chip flush with a surface of the substrate. The device includes a cover that covers the substrate and the first optoelectronic chip. The cover comprises a cavity above a first optical transduction region of the first optoelectronic chip. The device also includes a second optoelectronic chip having a second optical transduction region spaced apart from the first optical transduction region and the cavity continues above the second optical transduction region.

公开(公告)号：US20190355674A1

公开(公告)日：2019-11-21

申请号：US16411960

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US20230164905A1

公开(公告)日：2023-05-25

申请号：US17982913

申请日：2022-11-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0212 ,  H05K1/144 ,  H05K2201/06

Abstract: An electronic circuit includes an upper substrate and a lower substrate. An electronic integrated circuit chip is positioned between the upper and lower substrates. The chip includes contact elements coupled to the upper substrate. A first region made of a first material is arranged between the chip and a heat transfer area crossing the lower substrate. A second region filled with a second material couples the lower and upper substrates and laterally surrounds the first region. The first material has a thermal conductivity greater than a thermal conductivity of the second material.

公开(公告)号：US20220367330A1

公开(公告)日：2022-11-17

申请号：US17878436

申请日：2022-08-01

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Fabien QUERCIA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

公开(公告)号：US20210135038A1

公开(公告)日：2021-05-06

申请号：US17071694

申请日：2020-10-15

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Remi BRECHIGNAC ,  Jean-Michel RIVIERE

IPC: H01L31/16 ,  H01L23/00

Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.