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    MEMORY CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    5.
    发明申请
    MEMORY CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20250024690A1

    公开(公告)日：2025-01-16

    申请号：US18434423

    申请日：2024-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JEON IL LEE

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A memory chip includes a cell chip and a core-periphery chip, which are vertically stacked and are electrically connected to each other. The cell chip includes cell regions, each of which includes a memory cell layer. The core-periphery chip includes a core group region and a peripheral region which are adjacent to each other in a first direction. The core group region includes core regions arranged in a line in a second direction intersecting the first direction. Each of the core regions includes a core bank including a core circuit, and a neural processing unit (NPU) block including an NPU.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240015981A1

    公开(公告)日：2024-01-11

    申请号：US18132196

    申请日：2023-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JEON IL LEE ,  SERYEUN YANG ,  HYERAN LEE

    IPC: H10B51/30 ,  H10B51/20 ,  H10B51/40

    CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B51/40

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a bit line that extends in a first direction; first and second word lines that extend in a second direction and cross the bit line; an active pattern on the bit line between the first and second word lines, the active pattern including first second vertical parts that are opposite to each other, and a horizontal part that extends between the first and second vertical parts; a first data storage pattern between the first word line and the first vertical part of the active pattern; a second data storage pattern between the second word line and the second vertical part of the active pattern; and a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250107100A1

    公开(公告)日：2025-03-27

    申请号：US18639473

    申请日：2024-04-18

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： JEON IL LEE ,  YOUNGIN GOH

    IPC: H10B53/30

    Abstract: A semiconductor memory device includes: a device isolation pattern in a semiconductor substrate and defining an active pattern extending in a first direction; a bit line crossing the active pattern on the semiconductor substrate and extending in a second direction forming an acute angle with the first direction; a word line extending across the active pattern in a third direction intersecting the second direction and extending into the semiconductor substrate; electrode plates vertically stacked on the bit line; a common electrode pattern extending through the electrode plates to the active pattern on one side of the bit line; and a ferroelectric pattern between the common electrode pattern and the electrode plates. The bit line is in contact with an upper surface of the active pattern and an upper surface of the device isolation pattern.

    SEMICONDUCTOR DEVICES
    8.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240244847A1

    公开(公告)日：2024-07-18

    申请号：US18243726

    申请日：2023-09-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  JEON IL LEE ,  DAEWON HA

    IPC: H10B51/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

    CPC classification number: H10B51/20 ,  H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

    Abstract: A semiconductor device may include first stacks and second stacks, which are alternately disposed on a substrate in a first direction parallel to a top surface of the substrate, and first pads and second pads connecting the first stacks to the second stacks. Each of the first and second stacks may include a gate electrode, channel patterns, which enclose a side surface of the gate electrode and are spaced apart from each other, and first and second conductive lines connected to a corresponding channel pattern. The first and second conductive lines of the second stack may be disposed to be adjacent to the first and second conductive lines, respectively, of the first stack. The first and second pads may be connected to the first and second conductive lines, respectively, of the first and second stacks.

    Plasma Treatment Apparatus and Method of Fabricating Semiconductor Device Using the Same
    9.
    发明申请
    Plasma Treatment Apparatus and Method of Fabricating Semiconductor Device Using the Same 审中-公开

    公开(公告)号：US20190122903A1

    公开(公告)日：2019-04-25

    申请号：US15972350

    申请日：2018-05-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEUNG BO SHIM ,  HYUK KIM ,  SUN TAEK LIM ,  JAE MYUNG CHOE ,  JEON IL LEE ,  SUNG-IL CHO

    IPC: H01L21/67 ,  H01L21/683 ,  H01J37/32 ,  H01L21/3065

    Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

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