中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.013 seconds)

    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190164922A1

    公开(公告)日：2019-05-30

    申请号：US16244661

    申请日：2019-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-nee JANG ,  KyungSeon HWANG ,  SunWon KANG

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56

    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20200035649A1

    公开(公告)日：2020-01-30

    申请号：US16376440

    申请日：2019-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-nee JANG ,  Nam-gyu BAEK ,  Yun-rae CHO ,  Seung-hun HAN

    IPC: H01L25/065

    Abstract: A semiconductor package includes a package substrate, a plurality of external connections under the package substrate, a master chip on the package substrate, at least one slave chip on the master chip, a plurality of first bumps and a plurality of second bumps between the package substrate and the master chip, and a plurality of wires connecting the package substrate to the at least one slave chip. The package substrate includes a plurality of first paths connecting the plurality of first bumps to the plurality of external connections and a plurality of second paths connecting the plurality of second bumps to the plurality of wires. An upper surface of the package substrate includes a first edge and a second edge that extend in a first direction and a third edge and a fourth edge that extend in a second direction.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装

    公开(公告)号：US20140103523A1

    公开(公告)日：2014-04-17

    申请号：US14045881

    申请日：2013-10-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-gwon JANG ,  Young-lyong KIM ,  Jin-woo PARK ,  Ae-nee JANG

    IPC: H01L23/498

    CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/15311

    Abstract: A semiconductor package including a lower semiconductor chip, and an upper semiconductor chip flip-chip bonded on the lower semiconductor chip may be provided. Each of the lower and upper semiconductor chips includes a first bonding pad formed on an active surface, which has a center line extending in a first direction, and a first rewire electrically connected to the first bonding pad, The first rewire includes first and second connection regions. The first and second connection regions face each other and are disposed at a same distance from the center line in a second direction, which is perpendicular to the first direction.

    Abstract translation: 可以提供包括下半导体芯片的半导体封装和结合在下半导体芯片上的上半导体芯片倒装芯片。 下半导体芯片和上半导体芯片中的每一个包括形成在有源表面上的第一焊盘，该焊盘具有沿第一方向延伸的中心线，以及电连接到第一焊盘的第一重新布线。第一布线包括第一和第二连接 地区。 第一连接区域和第二连接区域彼此面对，并且在与第一方向垂直的第二方向上以与中心线相同的距离设置。

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210183801A1

    公开(公告)日：2021-06-17

    申请号：US17189405

    申请日：2021-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-nee JANG ,  KyungSeon HWANG ,  SunWon KANG

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48

    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

Patent Agency Ranking