公开(公告)号：US11942128B2

公开(公告)日：2024-03-26

申请号：US17576047

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Whankyun Kim ,  Jeong-Heon Park ,  Heeju Shin ,  Youngjun Cho ,  Joonmyoung Lee ,  Junho Jeong

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed is a magnetic memory device including a pinned magnetic pattern and a free magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a top electrode on the free magnetic pattern, and a capping pattern between the free magnetic pattern and the top electrode. The capping pattern includes a lower capping pattern, an upper capping pattern between the lower capping pattern and the top electrode, a first non-magnetic pattern between the lower capping pattern and the upper capping pattern, and a second non-magnetic pattern between the first non-magnetic pattern and the upper capping pattern. Each of the lower capping pattern and the upper capping pattern includes a non-magnetic metal. The first non-magnetic pattern and the second non-magnetic pattern include different metals from each other.

公开(公告)号：US12286707B2

公开(公告)日：2025-04-29

申请号：US17487088

申请日：2021-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Jeongheon Park ,  Junho Jeong

IPC: C23C14/56 ,  C23C14/08 ,  C23C16/40 ,  C23C16/54 ,  H01L21/67 ,  H10N50/01

Abstract: An apparatus for manufacturing a semiconductor device includes first and second process chambers in a first row in a first direction, third and fourth process chambers in a second row in the first direction, the third and fourth process chambers being spaced apart from the first and second process chambers in a second direction, and the first and third process chambers being arranged in parallel in the second direction to perform a same process, a load-lock chamber at one side of the first to fourth process chambers in the first direction, and first and second transfer chambers directly connected to each other in a third row in the first direction, the third row being between the first and second rows, and each of the first and second transfer chambers including a transfer unit to transfer a semiconductor substrate between the first to fourth process chambers and the load-lock chamber.

公开(公告)号：US11730064B2

公开(公告)日：2023-08-15

申请号：US16950009

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Chul Lee ,  Whankyun Kim ,  Joonmyoung Lee ,  Junho Jeong

IPC: H10N52/80 ,  G11C11/18 ,  G11C11/16 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10B61/22 ,  H10N52/00 ,  H10N52/01

Abstract: A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.

公开(公告)号：US10957845B2

公开(公告)日：2021-03-23

申请号：US16442991

申请日：2019-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsun Noh ,  Juhyun Kim ,  Whankyun Kim

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Provided are magnetic memory devices and method of fabricating the same. The magnetic memory device includes a magnetic tunnel junction pattern disposed on a substrate and including a free layer, a tunnel barrier layer and a pinned layer which are sequentially stacked, and a first spin-orbit torque (SOT) line being in contact with a first sidewall of the free layer of the magnetic tunnel junction pattern.

公开(公告)号：US09825216B2

公开(公告)日：2017-11-21

申请号：US15244498

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hwan Park ,  Whankyun Kim ,  Keewon Kim ,  Youngman Jang

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.

公开(公告)号：US11834738B2

公开(公告)日：2023-12-05

申请号：US17956281

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Eunsun Noh ,  Jeong-heon Park ,  Junho Jeong

IPC: C23C14/54 ,  C23C14/00 ,  G11B5/851 ,  H10B61/00 ,  H10N50/01

CPC classification number: C23C14/541 ,  C23C14/0057 ,  G11B5/851 ,  H10B61/00 ,  H10N50/01

Abstract: A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.

公开(公告)号：US11127786B2

公开(公告)日：2021-09-21

申请号：US16556599

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Jeong-Heon Park ,  Woo Chang Lim ,  Junho Jeong

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10

Abstract: Disclosed is a magnetic memory device including a line pattern on a substrate, a magnetic tunnel junction pattern on the line pattern, and an upper conductive line that is spaced apart from the line pattern across the magnetic tunnel junction pattern and is connected to the magnetic tunnel junction pattern. The line pattern provides the magnetic tunnel junction pattern with spin-orbit torque. The line pattern includes a chalcogen-based topological insulator.

公开(公告)号：US10483456B2

公开(公告)日：2019-11-19

申请号：US16191727

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hwan Park ,  Whankyun Kim ,  Keewon Kim ,  Youngman Jang

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.

公开(公告)号：US09691967B2

公开(公告)日：2017-06-27

申请号：US15185693

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Kim ,  Whankyun Kim ,  Sechung Oh

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L43/08

Abstract: Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment.

公开(公告)号：US11535929B2

公开(公告)日：2022-12-27

申请号：US16898609

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Heon Park ,  Whankyun Kim ,  Sukhoon Kim ,  Junho Jeong

IPC: C23C14/46 ,  H01L21/687 ,  H01L21/67 ,  H01L21/677

Abstract: An ion beam deposition apparatus includes a substrate assembly to secure a substrate, a target assembly slanted with respect to the substrate assembly, the target assembly including a target with deposition materials, an ion gun to inject ion beams onto the target, such that ions of the deposition materials are discharged toward the substrate assembly to form a thin layer on the substrate, and a substrate heater to heat the substrate to a deposition temperature higher than a room temperature.