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    Resistive memory device and operation
    1.
    发明授权
    Resistive memory device and operation 有权
    电阻式存储器和操作

    公开(公告)号：US09437290B2

    公开(公告)日：2016-09-06

    申请号：US14631182

    申请日：2015-02-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Hyo-Jin Kwon ,  Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0033 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

    Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.

    Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。

    Memory device and method of operating the same
    3.
    发明授权
    Memory device and method of operating the same 有权
    存储器件及其操作方法

    公开(公告)号：US09530494B2

    公开(公告)日：2016-12-27

    申请号：US14697244

    申请日：2015-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Chi-Weon Yoon ,  Hyun-Kook Park ,  Hyo-Jin Kwon

    IPC: G11C16/10 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/10 ,  G11C2013/0092

    Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.

    Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。

    Resistive memory device and method of operating the same
    4.
    发明授权
    Resistive memory device and method of operating the same 有权
    电阻式存储器件及其操作方法

    公开(公告)号：US09183932B1

    公开(公告)日：2015-11-10

    申请号：US14685671

    申请日：2015-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Jin Kwon ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Yong-Kyu Lee ,  Hyun-Kook Park

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C11/1675 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/72

    Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.

    Abstract translation: 一种电阻式存储器件，包括布置在第一信号线和第二信号线彼此交叉的区域中的多个电阻性存储器单元，以及操作该电阻式存储器件的方法。 该方法包括从连接到未选择的存储单元的未选择的第一信号线中的第一行应用第一电压，其不与多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线相邻; 从与所选择的第一信号线相邻的未选择的第一信号线中施加低于第一电压的第二电压到第二线; 浮动未选择的第一条信号线; 以及将高于第一电压的第三电压施加到所选择的第一信号线。

    Resistive memory device and operating method
    6.
    发明授权
    Resistive memory device and operating method 有权
    电阻式存储器件及操作方法

    公开(公告)号：US09552878B2

    公开(公告)日：2017-01-24

    申请号：US15166679

    申请日：2016-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chi-Weon Yoon ,  Hyun-Kook Park ,  Dae-Seok Byeon

    IPC: G11C11/34 ,  G11C16/04 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

    Abstract translation: 操作存储器件的方法包括： 通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中 所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压 在第二设定写入间隔期间到第一信号线的第二电压。

    Sensing circuits and phase change memory devices including the same
    7.
    发明授权
    Sensing circuits and phase change memory devices including the same 有权
    感测电路和包括相同的相变存储器件

    公开(公告)号：US09058874B2

    公开(公告)日：2015-06-16

    申请号：US13781997

    申请日：2013-03-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Don Choi ,  Mu-Hui Park ,  Hyun-Kook Park ,  Ickhyun Song

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/0069 ,  G11C2213/72

    Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

    Abstract translation: 感测电路包括多个单元读取电流发生器，参考电流发生器和多个读出放大器。 每个单元读取电流发生器从多个存储器单元中的每一个生成单元读取电流。 参考电流发生器将单元读取电流相加以产生和电流。 每个读出放大器基于每个单元读取电流和平均电流来确定存储在每个存储器单元中的数据状态。 平均电流是根据和电流获得的。

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