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    Three-dimensional semiconductor memory devices
    1.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10784311B2

    公开(公告)日：2020-09-22

    申请号：US16503937

    申请日：2019-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Hui Park ,  Wooyeong Cho

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/535

    Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.

    Three-dimensional semiconductor memory devices
    2.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10388699B2

    公开(公告)日：2019-08-20

    申请号：US15586307

    申请日：2017-05-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Hui Park ,  Wooyeong Cho

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/535

    Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.

    Method of operating resistive memory device reducing read disturbance
    3.
    发明授权
    Method of operating resistive memory device reducing read disturbance 有权

    公开(公告)号：US10770138B2

    公开(公告)日：2020-09-08

    申请号：US16721372

    申请日：2019-12-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hee-Won Kim ,  Mu-Hui Park

    IPC: G11C13/00 ,  G11C11/16 ,  G11C11/00

    Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

    Method of operating resistive memory device reducing read disturbance
    4.
    发明授权
    Method of operating resistive memory device reducing read disturbance 有权

    公开(公告)号：US10546637B2

    公开(公告)日：2020-01-28

    申请号：US16037109

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hee-Won Kim ,  Mu-Hui Park

    IPC: G11C13/00 ,  G11C11/16 ,  G11C11/00

    Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

    Nonvolatile memory device having resistive memory cell and method sensing data in same
    6.
    发明授权
    Nonvolatile memory device having resistive memory cell and method sensing data in same 有权
    具有电阻性存储单元和方法感测数据的非易失性存储器件

    公开(公告)号：US09368201B2

    公开(公告)日：2016-06-14

    申请号：US14494806

    申请日：2014-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Hui Park

    IPC: G11C13/00 ,  G11C16/26 ,  G11C7/06 ,  G11C5/06 ,  G11C11/56 ,  G11C7/14

    CPC classification number: G11C13/004 ,  G11C7/14 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/26 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/71

    Abstract: A method of sensing multi-bit data stored in a resistive memory cell includes; determining a resistive value range for the memory cell by performing a first read operation using a first read voltage and a first reference current, determining whether the multi-bit data stored in the resistive memory cell has a first program state, upon determining that the multi-bit data stored does not have the first program state, selecting a second read voltage different from the first read voltage in response to the resistive value range of the resistive memory cell, and using the second read voltage to again determine whether the multi-bit data stored in the resistive memory cell has the first program state.

    Abstract translation: 一种感测存储在电阻式存储器单元中的多位数据的方法包括： 通过使用第一读取电压和第一参考电流执行第一读取操作来确定存储器单元的电阻值范围，确定存储在电阻性存储单元中的多位数据是否具有第一编程状态， 存储的位数据不具有第一编程状态，响应于电阻性存储单元的电阻值范围选择与第一读取电压不同的第二读取电压，并且使用第二读取电压再次确定多位 存储在电阻性存储单元中的数据具有第一编程状态。

    Sensing circuits and phase change memory devices including the same
    10.
    发明授权
    Sensing circuits and phase change memory devices including the same 有权
    感测电路和包括相同的相变存储器件

    公开(公告)号：US09058874B2

    公开(公告)日：2015-06-16

    申请号：US13781997

    申请日：2013-03-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Don Choi ,  Mu-Hui Park ,  Hyun-Kook Park ,  Ickhyun Song

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/0069 ,  G11C2213/72

    Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

    Abstract translation: 感测电路包括多个单元读取电流发生器，参考电流发生器和多个读出放大器。 每个单元读取电流发生器从多个存储器单元中的每一个生成单元读取电流。 参考电流发生器将单元读取电流相加以产生和电流。 每个读出放大器基于每个单元读取电流和平均电流来确定存储在每个存储器单元中的数据状态。 平均电流是根据和电流获得的。

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