公开(公告)号：US20230420374A1

公开(公告)日：2023-12-28

申请号：US18303380

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Chul CHOI ,  Sang Hyun LEE ,  Un-Byoung KANG ,  Jung Hoon KANG

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/5383 ,  H01L25/16 ,  H01L23/49816 ,  H01L25/105

Abstract: A semiconductor package includes a package substrate having a first side and an opposite second side, a semiconductor chip on the first side of the package substrate, a capacitor on the second side of the package substrate, a plurality of connecting terminals on the second side of the package substrate, and a metal line within a trench in the package substrate. The trench extends in a first direction, and the metal line is between the capacitor and the plurality of connecting terminals. The metal line is spaced apart from the capacitor in a second direction that is transverse to the first direction, and a distance between the metal line and the capacitor is 100 μm or more and 1000 μm or less.

公开(公告)号：US20130181343A1

公开(公告)日：2013-07-18

申请号：US13653727

申请日：2012-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Seok AHN ,  Sang-Won KIM ,  Young-Sang CHO ,  Kwang-Chul CHOI ,  Sung-Eun PYO

IPC: H01L21/78 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A multi-chip package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first active surface. The second semiconductor chip has a second active surface facing the first active surface. The second active surface is electrically connected with the first active surfaceand the first active surface of the first semiconductor chip and the second active surface of the second semiconductor chip are bonded to each other without an adhesive.

Abstract translation: 多芯片封装包括第一半导体芯片和第二半导体芯片。 第一半导体芯片具有第一有源表面。 第二半导体芯片具有面向第一有源表面的第二有源表面。 第二有源表面与第一有源表面电连接，第一半导体芯片的第一有源表面和第二半导体芯片的第二有源表面彼此结合，而无需粘合剂。

公开(公告)号：US20160093518A1

公开(公告)日：2016-03-31

申请号：US14788783

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Dong JUNG ,  Jung-Hwan KIM ,  Dong-Gil LEE ,  Tae-Je CHO ,  Kwang-Chul CHOI

IPC: H01L21/67 ,  B32B43/00

CPC classification number: H01L21/67115 ,  B32B38/10 ,  B32B41/00 ,  B32B43/006 ,  B32B2250/02 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67253 ,  H01L2221/68381 ,  H01L2224/98 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Abstract translation: 提供了一种用于剥离晶片支撑系统的引发剂和方法。 用于剥离晶片支撑系统的启动器包括具有上表面的旋转卡盘，其上包括载体晶片的晶片支撑系统（WSS），器件晶片和用于将载体晶片和器件晶片接合的胶层 彼此坐下来旋转晶片支撑系统，检测模块检测胶层的高度和厚度;以及激光模块，其通过用激光照射胶层的侧表面而在胶层上产生断裂部分 胶层的高度和厚度的基础。

公开(公告)号：US20130299969A1

公开(公告)日：2013-11-14

申请号：US13835969

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won KIM ,  Kwang-Chul CHOI ,  Hyun-Jung SONG ,  Cha-Jea JO ,  Eun-Kyoung CHOI ,  Ji-Seok HONG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.

Abstract translation: 半导体封装包括第一半导体芯片，第二半导体芯片和密封构件。 第一半导体芯片包括具有与第一表面相对的第一表面和第二表面的基板，并且具有从第二表面以预定深度延伸的开口，以及从厚度方向从第一表面延伸的多个贯穿电极 通孔的端部通过开口的底表面露出。 第二半导体芯片被容纳在开口中并安装在开口的底表面上。 密封构件覆盖开口中的第二半导体芯片。