Abstract:
A method of operating a memory device including a plurality of memory cells is provided. The method includes receiving a first write command, determining whether a target memory cell is deteriorated or not, in response to the first write command, and writing the second data by selectively erasing the target memory cell according to a result of the determination and by programming the target memory cell.
Abstract:
A flash memory system includes; a controller that determines at least one parameter related to data reliability based on temperature information and generates a control signal based on the at least one parameter; and a memory device that comprises one or more memory cell arrays and provides the controller with read data corresponding to a read command received from the controller.
Abstract:
Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.
Abstract:
A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
Abstract:
A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
Abstract:
A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.
Abstract:
An application specific integrated circuit (ASIC) tangibly encodes a program of instructions executable by the integrated circuit to perform a method for fast Chase decoding of generalized Reed-Solomon (GRS) codes. The method includes using outputs of a syndrome-based hard-decision (HD) algorithm to find an initial Groebner basis G for a solution module of a key equation, upon failure of HD decoding of a GRS codeword received by the ASIC from a communication channel; traversing a tree of error patterns on a plurality of unreliable coordinates to adjoin a next weak coordinate, where vertices of the tree of error patterns correspond to error patterns, and edges connect a parent error pattern to a child error pattern having exactly one additional non-zero value, to find a Groebner basis for each adjoining error location; and outputting an estimated transmitted codeword when a correct error vector has been found.
Abstract:
A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.
Abstract:
A memory device, a memory system, and an operating method of the memory system is provided. The operating method includes operations of transmitting an authentication request to a memory device using a memory controller; converting the authentication request to a first address using the memory device; processing authentication data that corresponds to the first address and indicates a physical characteristic of the memory device and transmitting the authentication data as an authentication response to the authentication request to the memory controller using the memory device; and verifying whether the authentication response received from the memory device is an authentication response to the authentication request using the memory controller.
Abstract:
A method is provided for determining a deterioration condition of a memory device. The method includes calculating first information corresponding to a number of bits having a first logic value from data obtained by performing a first read operation on target storage region of the memory device using a first reference voltage as a read voltage, and calculating second information corresponding to a number of bits having a second logic value from data obtained by performing a second read operation on the target storage region using a second reference voltage as the read voltage. A deterioration condition of the target storage region is determined based on the first and second information. The first reference voltage is less than a first read voltage by which an erase state of the memory device is distinguished from an adjacent program state, and the second reference voltage is higher than the first read voltage.