SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器系统,半导体存储器件和操作半导体存储器件的方法

    公开(公告)号:US20170053683A1

    公开(公告)日:2017-02-23

    申请号:US15198564

    申请日:2016-06-30

    Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

    Abstract translation: 本发明构思的半导体器件包括:定时电路,被配置为从外部设备接收第一脉冲宽度的第一定时信号,并输出第二定时信号,该第二定时信号具有从第二脉冲宽度逐渐减小的脉冲宽度 第一定时信号的脉冲宽度和接收第二定时信号的数据输入/输出电路,并且与第二定时信号同步地将数据输出到外部设备。

    SEMICONDUCTOR MEMORY MODULE INCLUDING NONVOLATILE MEMORY DEVICES

    公开(公告)号:US20200042232A1

    公开(公告)日:2020-02-06

    申请号:US16390077

    申请日:2019-04-22

    Abstract: A semiconductor memory module includes data buffers that exchange first data signals with an external device, nonvolatile memory devices that are respectively connected to the data buffers through data lines, and a controller connected to the data lines. The controller receives an address, a command, and a control signal from the external device, and depending on the address, the command, and the control signal, the controller controls the data buffers through first control lines and controls the nonvolatile memory devices through second control lines.

    NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME 有权
    非易失性存储器件和具有该存储器件的存储器件

    公开(公告)号:US20150348605A1

    公开(公告)日:2015-12-03

    申请号:US14600366

    申请日:2015-01-20

    Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

    Abstract translation: 非易失性存储器件包括数据通路; 以及包括连接到数据路径的多个寄存器的FIFO存储器。 多个寄存器响应于数据路径输入时钟顺序地从数据路径接收数据,并且响应于数据路径输出时钟顺序地将接收的数据输出到输入/输出焊盘。 数据路径输出时钟是通过延迟数据通道输入时钟而产生的时钟,只要延迟时间。

    METHOD OF SHAPING A STROBE SIGNAL, A DATA STORAGE SYSTEM AND STROBE SIGNAL SHAPING DEVICE
    9.
    发明申请
    METHOD OF SHAPING A STROBE SIGNAL, A DATA STORAGE SYSTEM AND STROBE SIGNAL SHAPING DEVICE 有权
    形成行走信号的方法,数据存储系统和结构信号形成装置

    公开(公告)号:US20150294730A1

    公开(公告)日:2015-10-15

    申请号:US14600353

    申请日:2015-01-20

    CPC classification number: G11C16/26 G11C16/30 G11C16/32

    Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

    Abstract translation: 数据存储系统的选通信号整形方法包括接收选通信号; 当在预定时间段内空闲或暂停之后接收到选通信号时,提升选通信号的第一时钟边缘部分; 并且返回到相对于选通信号的第二时钟边缘部分关闭升压的操作模式。

Patent Agency Ranking