公开(公告)号：US20120032247A1

公开(公告)日：2012-02-09

申请号：US13197263

申请日：2011-08-03

申请人： Satoshi NAGASHIMA ,  Junya Fujita ,  Hideyuki Yamawaki ,  Masahiro Kiyotoshi ,  Hisataka Meguro

发明人： Satoshi NAGASHIMA ,  Junya Fujita ,  Hideyuki Yamawaki ,  Masahiro Kiyotoshi ,  Hisataka Meguro

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括通过在沟道半导体层上依次层叠栅绝缘膜，浮栅电极，电极间绝缘膜和控制栅电极而获得的存储单元晶体管。 控制栅电极具有通过顺序堆叠半导体膜，硅化物相变抑制层和硅化物膜而获得的结构。 此外，硅化物相变抑制层包括在1×1020〜5×1021 [原子/ cm3]的浓度范围内掺杂有C，F和N中的至少一种的多晶硅膜。

公开(公告)号：US08748965B2

公开(公告)日：2014-06-10

申请号：US13197263

申请日：2011-08-03

申请人： Satoshi Nagashima ,  Junya Fujita ,  Hideyuki Yamawaki ,  Masahiro Kiyotoshi ,  Hisataka Meguro

发明人： Satoshi Nagashima ,  Junya Fujita ,  Hideyuki Yamawaki ,  Masahiro Kiyotoshi ,  Hisataka Meguro

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括通过在沟道半导体层上依次层叠栅绝缘膜，浮栅电极，电极间绝缘膜和控制栅电极而获得的存储单元晶体管。 控制栅电极具有通过顺序堆叠半导体膜，硅化物相变抑制层和硅化物膜而获得的结构。 此外，硅化物相变抑制层包括在1×1020〜5×1021 [原子/ cm3]的浓度范围内掺杂有C，F和N中的至少一种的多晶硅膜。

公开(公告)号：US09087715B2

公开(公告)日：2015-07-21

申请号：US13547645

申请日：2012-07-12

申请人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

发明人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

IPC分类号： H01L27/115 ,  H01L27/088 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/24 ,  G11C16/04 ,  H01L29/66 ,  H01L29/68 ,  H01L29/788 ,  H01L29/792 ,  G11C16/10 ,  H01L29/82

CPC分类号： H01L27/088 ,  G11C16/04 ,  G11C16/10 ,  H01L21/02367 ,  H01L21/265 ,  H01L21/32051 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/685 ,  H01L29/788 ,  H01L29/792 ,  H01L29/82

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。 结构和梁中的每一个包括沿垂直方向堆叠的半导体层。 梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

公开(公告)号：US20130032873A1

公开(公告)日：2013-02-07

申请号：US13326972

申请日：2011-12-15

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/7926 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱和多个存储单元。 层叠体包括设置在栅电极之间的多个层叠栅电极和电极间绝缘层。 半导体柱穿过堆叠体。 多个存储单元沿层叠方向设置。 存储单元包括通过气隙设置在半导体柱和栅电极之间的电荷陷阱层。 块绝缘层设置在电荷陷阱层和栅电极之间。 多个存储单元中的每一个设置有被配置为保持电荷陷阱层和半导体柱之间的气隙距离的支撑部分。

公开(公告)号：US08143146B2

公开(公告)日：2012-03-27

申请号：US12469872

申请日：2009-05-21

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

摘要： A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated.

摘要翻译： 提供了一种制造具有堆叠在其中的多个单元存储层的非易失性存储装置的方法。 每个单元存储层包括：沿第一方向延伸的第一互连; 沿第二方向延伸的第二互连; 记录单元，夹在第一和第二互连之间，并且能够响应于通过第一和第二互连提供的电流在第一状态和第二状态之间可逆地转换; 以及夹在所述第一布线和所述记录单元之间并且包括p型和n型杂质中的至少一种的整流元件。 在该方法中，在多个单元存储层中使用的第一互连，第二互连，记录单元以及包含p型和n型杂质中的至少一种的非晶材料层形成在温度 低于无定形材料基本上结晶的温度。 在多个单元存储层中使用的非晶材料同时结晶化，并且包含在多个单元存储层中使用的非晶材料中的杂质同时被激活。

公开(公告)号：US08114755B2

公开(公告)日：2012-02-14

申请号：US12146143

申请日：2008-06-25

申请人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

发明人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

IPC分类号： H01L21/76

CPC分类号： H01L21/764

摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

公开(公告)号：US20110147822A1

公开(公告)日：2011-06-23

申请号：US12929894

申请日：2011-02-23

申请人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

发明人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L29/40114 ,  H01L29/66825

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

公开(公告)号：US20100171164A1

公开(公告)日：2010-07-08

申请号：US12659703

申请日：2010-03-17

申请人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

发明人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.

摘要翻译： 一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器 电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个 设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面 材料。

公开(公告)号：US07538047B2

公开(公告)日：2009-05-26

申请号：US11451519

申请日：2006-06-13

申请人： Atsuko Kawasaki ,  Takeshi Hoshi ,  Masahiro Kiyotoshi ,  Takatoshi Ono ,  Yoshihiro Ogawa ,  Kaori Umezawa

发明人： Atsuko Kawasaki ,  Takeshi Hoshi ,  Masahiro Kiyotoshi ,  Takatoshi Ono ,  Yoshihiro Ogawa ,  Kaori Umezawa

IPC分类号： H01L21/469

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： A method of manufacturing a semiconductor device includes forming a trench for isolation on a surface of a substrate including a semiconductor substrate, filling the trench with a solution containing a perhydrosilazane polymer by applying the solution on the substrate, converting the solution into a film containing the perhydrosilazane polymer by heating the solution, and converting the film into a silicon dioxide film including heating the film at a first temperature in an atmosphere containing vapor, and heating the film heated at the first temperature at a second temperature lower than the first temperature in an atmosphere containing vapor or in pure water.

摘要翻译： 一种制造半导体器件的方法包括在包括半导体衬底的衬底的表面上形成用于隔离的沟槽，通过将溶液涂覆在衬底上，用含有全氢硅氮烷聚合物的溶液填充沟槽，将溶液转化为含有 通过加热溶液，将膜转化为二氧化硅膜，包括在含有蒸气的气氛中的第一温度下加热该膜，并且在第一温度下在比第一温度低的温度下加热第一温度的膜， 含有蒸汽或纯水的气氛。

公开(公告)号：US07514338B2

公开(公告)日：2009-04-07

申请号：US11544747

申请日：2006-10-10

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi

IPC分类号： H01L21/76

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a first atmosphere, which contains oxygen, and whose oxygen partial pressure is set in a range of 16 to 48 Torr, oxidizing the polymer film in a second atmosphere containing water vapor to form an oxide film containing a silicon oxide as a main component, after holding the work piece in the first atmosphere, and removing an upper portion of the oxide film to remain a lower portion of the oxide film in the trench.

摘要翻译： 一种制造半导体器件的方法，包括在其主表面侧准备具有沟槽的工件，在工件的主表面上形成含有含有硅，氢和氮的聚合物的聚合物膜，将工件与 聚合物膜在含有氧的第一气氛中，其氧分压设定在16〜48托的范围内，在含有水蒸气的第二气氛中氧化聚合物膜，形成含有氧化硅为主要的氧化膜 在第一气氛中保持工件之后，除去氧化膜的上部以保留在沟槽中的氧化膜的下部。