公开(公告)号：US20250151393A1

公开(公告)日：2025-05-08

申请号：US19008793

申请日：2025-01-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yoshiharu HIRAKATA ,  Takashi HAMADA ,  Kohei YOKOYAMA ,  Yasuhiro JINBO ,  Tetsuji ISHITANI ,  Daisuke KUBOTA

IPC: H10D86/01 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  H10D30/67 ,  H10D86/40 ,  H10D86/60 ,  H10K50/842 ,  H10K50/844 ,  H10K59/38 ,  H10K59/40 ,  H10K71/50 ,  H10K102/00

Abstract: A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.

公开(公告)号：US20250076697A1

公开(公告)日：2025-03-06

申请号：US18954090

申请日：2024-11-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshiharu Hirakata ,  Tetsuji ISHITANI ,  Daisuke KUBOTA ,  Ryo HATSUMI ,  Masaru NAKANO ,  Takashi HAMADA

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/1362

Abstract: A display device including a peripheral circuit portion with high operation stability. The display device includes a first substrate and a second substrate. A first insulating layer is on a first plane of the first substrate, and a second insulating layer is on a first plane of the second substrate. An area of the first plane of the first substrate is the same as an area of the first plane of the second substrate. The first plane of the first substrate and the first plane of the second substrate face each other. A bonding layer is between the first insulating layer and the second insulating layer. A protection film is in contact with the first substrate, the first insulating layer, the bonding layer, the second insulating layer, and the second substrate.

公开(公告)号：US20160293766A1

公开(公告)日：2016-10-06

申请号：US15175183

申请日：2016-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Hiroaki HONDA ,  Takashi HAMADA

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/02334 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

Abstract translation: 准备具有绝缘表面的基板; 在基板上形成包括第一氧化物半导体层和第二氧化物半导体层的层叠膜; 在层叠膜的一部分上形成掩模层，然后进行干法蚀刻处理，从而除去保留有掩模层的区域，在其余的侧面形成反应产物 叠片 去除掩模层后，通过湿蚀刻处理去除反应产物; 源极电极和漏电极形成在堆叠膜上; 并且第三氧化物半导体层，栅极绝缘膜和栅极电极按顺序层叠并形成在堆叠膜上，以及源电极和漏电极。

公开(公告)号：US20240322046A1

公开(公告)日：2024-09-26

申请号：US18675249

申请日：2024-05-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Satoshi TORIUMI ,  Takashi HAMADA ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Yuji ASANO ,  Ryunosuke HONDA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H10B41/70

CPC classification number: H01L29/7869 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/14645 ,  H01L27/14649 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78648 ,  H01L29/78696 ,  H10B41/70

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

公开(公告)号：US20240224616A1

公开(公告)日：2024-07-04

申请号：US18569342

申请日：2022-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuichi YANAGISAWA ,  Kenichi OKAZAKI ,  Takashi HAMADA ,  Shinya SASAGAWA

IPC: H10K59/122

CPC classification number: H10K59/122

Abstract: A display apparatus with high resolution is provided. A display apparatus which can achieve high color reproducibility is provided. A display apparatus with high luminance is provided. A highly reliable display apparatus is provided. The display apparatus includes a first insulating layer, a first conductive layer provided in an opening of the first insulating layer, a first EL layer over the first conductive layer and the first insulating layer, a second insulating layer in contact with a side surface of the first EL layer and a top surface of the first insulating layer, and a second conductive layer over the first EL layer and the second insulating layer.

公开(公告)号：US20240057403A1

公开(公告)日：2024-02-15

申请号：US18266645

申请日：2021-12-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuichi YANAGISAWA ,  Shinya SASAGAWA ,  Takashi HAMADA

IPC: H10K59/124

CPC classification number: H10K59/124

Abstract: A highly reliable display device is provided. The display device includes a transistor over a substrate, a first insulating layer over the transistor, a second insulating layer over the first insulating layer, a plug placed to be embedded in the first insulating layer and the second insulating layer, and a light-emitting element over the second insulating layer. The light-emitting element includes a first conductive layer, an EL layer over the first conductive layer, and a second conductive layer over the EL layer. The plug electrically connects one of a source and a drain of the transistor to the first conductive layer. The second insulating layer has higher capability of inhibiting hydrogen diffusion than the first insulating layer.

公开(公告)号：US20170288064A1

公开(公告)日：2017-10-05

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/46 ,  H01L29/66 ,  H01L21/425

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US20170062619A1

公开(公告)日：2017-03-02

申请号：US15235242

申请日：2016-08-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Takashi HAMADA ,  Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/465 ,  H01L29/423 ,  H01L21/4757

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供具有高导通状态电流的晶体管。 提供包括晶体管的半导体器件。 提供了具有高集成度的半导体器件。 一种包括氧化物半导体的半导体器件; 第二绝缘体; 第二导体 第三导体; 第四导体 第五个指挥 嵌入在形成于第二绝缘体的开口部的第一导体和第一绝缘体，第二导​​体，第三导体，第四导体和第五导体; 第二导体的侧表面和底表面与第四导体接触的区域; 以及第三导体的侧表面和底表面与第五导体接触的区域。

公开(公告)号：US20240088172A1

公开(公告)日：2024-03-14

申请号：US18512392

申请日：2023-11-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yoshiharu HIRAKATA ,  Takashi HAMADA ,  Kohei YOKOYAMA ,  Yasuhiro JINBO ,  Tetsuji ISHITANI ,  Daisuke KUBOTA

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H10K50/842

CPC classification number: H01L27/1262 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/1339 ,  G02F1/136213 ,  G02F1/1368 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H10K50/8426 ,  H10K50/8428 ,  H10K50/844

Abstract: A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.

公开(公告)号：US20240049562A1

公开(公告)日：2024-02-08

申请号：US18257617

申请日：2021-12-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuichi YANAGISAWA ,  Shinya SASAGAWA ,  Takashi HAMADA

IPC: H10K59/80 ,  H10K59/12

CPC classification number: H10K59/80518 ,  H10K59/1201 ,  H10K59/80517 ,  H10K59/35

Abstract: A display device with high resolution is provided. The display device includes a first conductor, a first insulator over the first conductor, a second conductor provided inside an opening of the first insulator, a first light-emitting layer in contact with a top surface of the second conductor and a top surface of the first insulator, and a third conductor in contact with a top surface of the first light-emitting layer.