公开(公告)号：US20170178968A1

公开(公告)日：2017-06-22

申请号：US15376408

申请日：2016-12-12

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L21/8234 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/02271 ,  H01L21/266 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/785

摘要： A method for manufacturing a semiconductor device having a shallow trench isolation structure includes providing a semiconductor substrate having first and second regions, multiple fins disposed on the first and second regions, and a hardmask layer on an upper surface of the fins, forming a first dielectric layer on the semiconductor substrate covering the fins, forming a first mask layer including an opening exposing a portion of the first dielectric layer between the first and second regions, implanting dopant ions into the exposed portion of the first dielectric layer, removing the first mask layer, and performing an etching process on the first dielectric layer to form a first isolation region between the first and second regions and a second isolation region between the fins. The doped portion has a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.

公开(公告)号：US20170117188A1

公开(公告)日：2017-04-27

申请号：US15284839

申请日：2016-10-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： FEI ZHOU

IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L21/324 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/66803

摘要： In various embodiments of the disclosed subject matter, a semiconductor structure, and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: providing a substrate; implanting first punch-through preventing ions into an NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into a PMOS region of the substrate to form a second implantation layer; etching the substrate to form first fin portions in the NMOS region, and second fin portions in the PMOS region, the remaining first implantation layer forms a first punch-through preventing layer, the remaining second implantation layer forms a second punch-through preventing layer; forming insulating structures between adjacent first fin portions and second fin portions; and performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.

公开(公告)号：US20170154827A1

公开(公告)日：2017-06-01

申请号：US15283239

申请日：2016-09-30

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： FEI ZHOU

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823892 ,  H01L21/26513 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0925 ,  H01L27/0927 ,  H01L27/0928 ,  H01L29/66803

摘要： A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

公开(公告)号：US20170125305A1

公开(公告)日：2017-05-04

申请号：US15332271

申请日：2016-10-24

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： FEI ZHOU

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L29/423 ,  H01L29/20 ,  H01L29/267 ,  H01L29/08 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L21/823857 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02244 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.

公开(公告)号：US20170117191A1

公开(公告)日：2017-04-27

申请号：US15283113

申请日：2016-09-30

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： FEI ZHOU

IPC分类号： H01L21/8238 ,  H01L21/285 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966

摘要： A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.

公开(公告)号：US20170365602A1

公开(公告)日：2017-12-21

申请号：US15471983

申请日：2017-03-28

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

摘要： A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.

公开(公告)号：US20170133489A1

公开(公告)日：2017-05-11

申请号：US15335248

申请日：2016-10-26

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： FEI ZHOU

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7856

摘要： A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a peripheral region of a substrate and a plurality of second fin structures in a core region of the substrate, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure together with each second dummy gate electrode layer, forming a first gate oxide layer on the exposed portion of each first fin structure, and then removing each second dummy gate oxide layer. The method further includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.

公开(公告)号：US20180337268A1

公开(公告)日：2018-11-22

申请号：US15925390

申请日：2018-03-19

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/66803 ,  H01L21/30625 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66871 ,  H01L29/785

摘要： A method of manufacturing a semiconductor device includes providing a semiconductor structure including a substrate, a semiconductor fin on the substrate, and a dummy gate structure on the semiconductor fin. The dummy gate structure includes a dummy gate dielectric layer on the semiconductor fin and a dummy gate on the dummy gate dielectric layer. The method also includes forming an interlayer dielectric layer on the semiconductor substrate, planarizing the interlayer dielectric layer to expose an upper surface of the dummy gate, and performing a first doping implant into the semiconductor fin through the dummy gate to form an anti-puncture region in the semiconductor fin. The anti-puncture region has an upper surface lower than an upper surface of a trench isolation portion surrounding the semiconductor fin to prevent a punch through of a source and drain, reducing a current leakage and parasitic capacitance of the semiconductor device.

公开(公告)号：US20180331099A1

公开(公告)日：2018-11-15

申请号：US15918644

申请日：2018-03-12

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L27/088 ,  H01L21/765 ,  H01L21/762 ,  H01L21/66 ,  H01L23/34

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/765 ,  H01L21/823437 ,  H01L21/823481 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/345

摘要： A semiconductor device includes a substrate, a semiconductor fin on the substrate, first and second MOS devices on the substrate, and a dummy gate structure on the semiconductor fin and between the first and second MOS devices. The first dummy gate structure is operative to electrically isolate the first MOS device from the second MOS device when a first potential is applied to the dummy gate structure and a second potential is applied to the substrate. The first MOS device includes a first gate structure on the semiconductor fin, a first source and a first drain on opposite sides of the first gate structure and partially in the semiconductor fin. The second MOS device includes a second gate structure on the semiconductor fin, a second source and a second drain on opposite sides of the second gate structure and partially in the semiconductor fin.

公开(公告)号：US20180315839A1

公开(公告)日：2018-11-01

申请号：US15918719

申请日：2018-03-12

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.