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公开(公告)号:US20060129701A1
公开(公告)日:2006-06-15
申请号:US11012316
申请日:2004-12-15
IPC分类号: G06F3/00
CPC分类号: G11C5/066
摘要: A technique includes sharing common external terminals of a memory device to communicate data and an address with the memory device for a given memory operation. Different sets of address bits indicative of the address are communicated over the common external terminals at different times.
摘要翻译: 一种技术包括共享存储器设备的公共外部终端以与给定存储器操作的存储器设备通信数据和地址。 指示地址的不同地址位组在不同的时间通过公共外部终端进行通信。
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公开(公告)号:US08782314B2
公开(公告)日:2014-07-15
申请号:US13249057
申请日:2011-09-29
申请人: Love Kothari , Mark Fullerton
发明人: Love Kothari , Mark Fullerton
CPC分类号: H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要: Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.
摘要翻译: 实施例包括用于在片上系统(SOC)中将中断传播到子系统的中断控制器的系统和方法。 中断提供给一个中断控制器,该中断控制器控制对包含多个子系统的SOC中特定子系统的中断访问。 SOC中的每个子系统对SOC中的其他子系统产生多个中断。 中断控制器处理多个中断并产生中断输出。 然后将中断输出发送到特定的子系统。
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公开(公告)号:US20130047023A1
公开(公告)日:2013-02-21
申请号:US13331874
申请日:2011-12-20
申请人: Paul Penzes , Mark Fullerton
发明人: Paul Penzes , Mark Fullerton
IPC分类号: G06F1/04
CPC分类号: H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要: Adaptive clocking schemes for synchronized on-chip functional Hocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example, in embodiments, the docking schemes allow for the capacity utilization of a logic path to be increased.
摘要翻译: 提供了同步片上功能Hocks的自适应时钟方案。 时钟方案使得可以根据信号路径传播延迟因温度,过程和电压变化而改变的同步时钟,例如在实施例中,对接方案允许增加逻辑路径的容量利用。
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4.
公开(公告)号:US08180996B2
公开(公告)日:2012-05-15
申请号:US12466996
申请日:2009-05-15
申请人: Mark Fullerton , Barry Evans
发明人: Mark Fullerton , Barry Evans
IPC分类号: G06F12/06
CPC分类号: G06F12/1081 , G06F12/1036
摘要: A distributed computing system that incorporates enhanced distributed storage and a universal address system and method are provided.
摘要翻译: 提供了一种结合增强分布式存储和通用地址系统和方法的分布式计算系统。
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公开(公告)号:USD617852S1
公开(公告)日:2010-06-15
申请号:US29344270
申请日:2009-09-25
申请人: Greg Fisher , Stacy Crawford , Mark Fullerton , Lee Fullerton
设计人: Greg Fisher , Stacy Crawford , Mark Fullerton , Lee Fullerton
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公开(公告)号:USD616508S1
公开(公告)日:2010-05-25
申请号:US29344274
申请日:2009-09-25
申请人: Greg Fisher , Stacy Crawford , Mark Fullerton , Lee Fullerton
设计人: Greg Fisher , Stacy Crawford , Mark Fullerton , Lee Fullerton
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公开(公告)号:US20070247182A1
公开(公告)日:2007-10-25
申请号:US11395871
申请日:2006-03-31
申请人: Timothy Beatty , Mark Fullerton , Tom Mozdzen
发明人: Timothy Beatty , Mark Fullerton , Tom Mozdzen
IPC分类号: H03K19/00
摘要: A protection circuit is disclosed, for preventing access to stored security key data after the security key is no longer used. The protection circuit performs operations on a programming circuit used to program a bit of the security key. The protection circuit prevents inspection of the security key bit, using several techniques. Subsequent inspection of the programming circuit does not reveal the value of the security key bit.
摘要翻译: 公开了一种用于在不再使用安全密钥之后防止对存储的安全密钥数据的访问的保护电路。 保护电路对用于编程安全密钥位的编程电路进行操作。 保护电路使用几种技术来防止对安全密钥位的检查。 对编程电路的后续检查不会显示安全密钥位的值。
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8.
公开(公告)号:US20060135094A1
公开(公告)日:2006-06-22
申请号:US11014805
申请日:2004-12-20
申请人: Amit Dor , Charles Roth , Mark Fullerton
发明人: Amit Dor , Charles Roth , Mark Fullerton
IPC分类号: H01Q11/12
CPC分类号: G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.
摘要翻译: 简而言之,是一种能够通过基于参考数根据电压值改变半导体器件的工作电压来管理半导体器件的功耗的半导体器件的电源管理系统的装置的方法。
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9.
公开(公告)号:US08575993B2
公开(公告)日:2013-11-05
申请号:US13247694
申请日:2011-09-28
申请人: Paul Penzes , Mark Fullerton
发明人: Paul Penzes , Mark Fullerton
IPC分类号: H01L35/00
CPC分类号: H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
摘要翻译: 某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。 可以看出,在这些半导体工艺中的某些中,高阈值晶体管可以运行的速度随着温度的降低而降低。 因此,实现高阈值晶体管的IC的总体处理速度通常受IC设计(或保证)以适当地起作用的最低温度的限制。 通过“预热”IC(或实现高阈值晶体管的IC的至少部分)来克服这种缺陷的系统和方法的实施例,使得IC可以以高于 在设计(或保证)设计IC(或保证)的给定最低温度下,将提供适当的功能。
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10.
公开(公告)号:US20130043927A1
公开(公告)日:2013-02-21
申请号:US13247694
申请日:2011-09-28
申请人: Paul PENZES , Mark Fullerton
发明人: Paul PENZES , Mark Fullerton
IPC分类号: H03K3/011
CPC分类号: H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
摘要翻译: 某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。 可以看出,在这些半导体工艺中的某些中,高阈值晶体管可以运行的速度随着温度的降低而降低。 因此,实现高阈值晶体管的IC的总体处理速度通常受IC设计(或保证)以适当地起作用的最低温度的限制。 通过预热IC(或实现高阈值晶体管的IC的至少一部分)来克服这种缺陷的系统和方法的实施例,使得IC可以以比将被加热的频率高(一次预热) 否则可能在设计(或保证)IC的给定最低温度下提供正确的功能。
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