公开(公告)号：US06740928B2

公开(公告)日：2004-05-25

申请号：US10350140

申请日：2003-01-24

申请人： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

发明人： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  G11C13/02 ,  G11C13/025 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7883

摘要： The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.

摘要翻译： 本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。 电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷 保持在电荷保持颗粒中。

公开(公告)号：US06548825B1

公开(公告)日：2003-04-15

申请号：US09587268

申请日：2000-06-05

申请人： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

发明人： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

IPC分类号： H01L310328

CPC分类号： B82Y10/00 ,  G11C13/02 ,  G11C13/025 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7883

摘要： The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.

摘要翻译： 本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。 电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷 保持在电荷保持颗粒中。

公开(公告)号：US08486788B2

公开(公告)日：2013-07-16

申请号：US13162310

申请日：2011-06-16

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20120104350A1

公开(公告)日：2012-05-03

申请号：US13379460

申请日：2011-04-26

申请人： Atsushi Himeno ,  Haruyuki Sorada ,  Takumi Mikawa

发明人： Atsushi Himeno ,  Haruyuki Sorada ,  Takumi Mikawa

IPC分类号： H01L27/26 ,  H01L47/00

CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1633

摘要： A step of forming, on a substrate (11), lower layer copper lines (18) each being shaped into a strip, a step of forming electrode seed layers (21) each being shaped into a strip, on the surfaces of the respective lower layer copper lines (18) using electroless plating, a step of forming interlayer insulating layer (19) above the electrode seed layers (21) and the substrate (11), a step of forming, in the interlayer insulating layer (19), memory cell holes (20), penetrating through the interlayer insulating layer (19) and extending to the electrode seed layers (21), a step of forming noble metal electrode layers (29) on the surfaces of the electrode seed layers (21) exposed in the respective memory cell holes (20) using the electroless plating, a step of forming, in the respective memory cell holes (20), variable resistance layers (23) connected to the noble electrode layers (29), and a step of forming, above the interlayer insulating layer (19) and the variable resistance layers (23), upper layer copper lines (24) each being shaped into a strip, connected to a corresponding one of the variable resistance layers (23), and crossing the lower layer copper lines (18), are included.

摘要翻译： 在基板（11）上形成各自被成形为条带的下层铜线（18）的步骤，在各自的下表面上形成各自成形为条带的电极种子层（21）的步骤 使用无电镀的层间铜线（18），在电极种子层（21）和基板（11）的上方形成层间绝缘层（19）的工序，在层间绝缘层（19） 穿过层间绝缘层（19）并延伸到电极种子层（21）的电池孔（20），在暴露于电极种子层（21）的表面上形成贵金属电极层（29）的步骤 使用无电镀的各个存储单元孔（20），在各个存储单元孔（20），连接到贵金属电极层（29）的可变电阻层（23）上形成步骤， 在层间绝缘层（19）和可变电阻层（23）之上， 上层铜线（24）各自被成形为条，连接到相应的一个可变电阻层（23）并与下层铜线（18）交叉。

公开(公告)号：US07235830B2

公开(公告)日：2007-06-26

申请号：US11260197

申请日：2005-10-28

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC分类号： H01L29/76

CPC分类号： H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

摘要翻译： 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US20050133834A1

公开(公告)日：2005-06-23

申请号：US10948747

申请日：2004-09-24

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US20050040436A1

公开(公告)日：2005-02-24

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L27/10

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US09012294B2

公开(公告)日：2015-04-21

申请号：US13812227

申请日：2011-07-26

申请人： Satoru Fujii ,  Takumi Mikawa ,  Haruyuki Sorada

发明人： Satoru Fujii ,  Takumi Mikawa ,  Haruyuki Sorada

IPC分类号： H01L45/00 ,  H01L21/20 ,  H01L27/10 ,  H01L27/24

CPC分类号： H01L45/1616 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/145 ,  H01L45/146

摘要： Each of the step of forming a first variable resistance layer (18a) and the step of forming a second variable resistance layer (18b) includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step of introducing a reactive gas to form a transition metal oxide after the second step; and a fourth step of removing the reactive gas after the third step. The step of forming the first variable resistance layer (18a) is performed in a state in which the substrate is kept at a temperature at which a self-decomposition reaction of the source gas does not occur. One or plural of conditions used for forming the second variable resistance layer (18b) is/are made different from the one or plural conditions used for forming the first variable resistance layer (18a), the conditions being the temperature of the substrate, an amount of the introduced source gas and an amount of the introduced reactive gas.

摘要翻译： 形成第一可变电阻层（18a）的步骤和形成第二可变电阻层（18b）的步骤包括执行一次或多次的循环，所述循环包括：引入由 含有过渡金属原子的分子; 在第一步骤之后除去源气体的第二步骤; 在第二步骤之后引入反应气体以形成过渡金属氧化物的第三步骤; 以及在第三步骤之后除去反应气体的第四步骤。 形成第一可变电阻层（18a）的步骤是在基板保持在不发生源气体的自分解反应的温度的状态下进行的。 使用于形成第二可变电阻层（18b）的一个或多个条件与用于形成第一可变电阻层（18a）的一个或多个条件不同，条件是基板的温度， 的引入源气体和一定量的引入的反应气体。

公开(公告)号：US08618526B2

公开(公告)日：2013-12-31

申请号：US13501228

申请日：2011-08-11

申请人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

发明人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

摘要： Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

摘要翻译： 提供一种能够抑制非易失性存储元件之间的初始击穿电压的不均匀性并且防止产量降低的非易失性存储器件及其制造方法。 非易失性存储器件包括具有堆叠层结构的非易失性存储元件（108），其中电阻变化层（106）平行于衬底（117）的主表面并被平坦化;以及电极（103） 连接到第一电极（105）或第二电极（107），以及插头（103）的端面（103）的与插头（103）和非易失性存储元件（108）连接在一起的区域， 平行于基板（117）的主表面的端面大于作为导电区域的第一过渡金属氧化物层（115）的截面的横截面积，横截面 平行于基板（117）的主表面。

公开(公告)号：US08581225B2

公开(公告)日：2013-11-12

申请号：US13379460

申请日：2011-04-26

申请人： Atsushi Himeno ,  Haruyuki Sorada ,  Takumi Mikawa

发明人： Atsushi Himeno ,  Haruyuki Sorada ,  Takumi Mikawa

IPC分类号： H01L27/26 ,  H01L47/00

CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1633

摘要： A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.

摘要翻译： 一种制造方法，包括在基板上形成各自成形为条状的下层铜线，在各下层铜线上形成各自成形为条状的电极种子层，使用化学镀，在上述铜层上形成层间绝缘层 电极种子层，在所述层间绝缘层中形成穿过所述层间绝缘层并延伸到所述电极种子层的存储单元孔，在使用所述无电解槽的各个存储单元孔中露出的所述电极种子层上形成贵金属电极层 在各个存储单元孔中电镀，形成连接到贵金属电极层的可变电阻层，并且在层间绝缘层和可变电阻层之上形成上层铜线，每条铜线被成形为带状，连接到相应的 一个可变电阻层，并穿过下层铜线。