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    NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请
    NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号：US20120205735A1

    公开(公告)日：2012-08-16

    申请号：US13404073

    申请日：2012-02-24

    申请人： Naoki YASUDA ,  Jun Fujiki

    发明人： Naoki YASUDA ,  Jun Fujiki

    IPC分类号： H01L27/115

    CPC分类号： H01L21/28282 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/792

    摘要： In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.

    摘要翻译： 在一个实施例中，提供了一种非易失性半导体存储装置。 该装置包括：多个非易失性存储单元。 每个非易失性存储单元包括：第一半导体层，包括第一源极区，第一漏极区和第一沟道区; 形成在所述第一沟道区上的块绝缘膜; 形成在所述块绝缘膜上的电荷存储层; 形成在电荷存储层上的隧道绝缘膜; 形成在所述隧道绝缘膜上并且包括第二源极区域，第二漏极区域和第二沟道区域的第二半导体层。 第二沟道区形成在隧道绝缘膜上，使得隧道绝缘膜位于第二源区和第二漏区之间。 第一沟道区的掺杂剂杂质浓度高于第二沟道区的掺杂剂杂质浓度。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME 失效
    非易失性半导体存储器件及其驱动方法

    公开(公告)号：US20100080062A1

    公开(公告)日：2010-04-01

    申请号：US12411746

    申请日：2009-03-26

    申请人： Jun Fujiki ,  Koichi Muraoka ,  Naoki Yasuda

    发明人： Jun Fujiki ,  Koichi Muraoka ,  Naoki Yasuda

    IPC分类号： G11C16/04 ,  H01L29/792 ,  G11C5/14 ,  G11C11/34

    CPC分类号： G11C16/26 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11565 ,  H01L27/11568

    摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second insulating film provided on the charge retention layer; and a semiconductor layer including a second channel provided on the second insulating film, and a source region and a drain region provided on both sides of the second channel.

    摘要翻译： 非易失性半导体存储器件包括：包括第一沟道的半导体衬底和设置在第一沟道两侧的源极区和漏极区; 设置在第一通道上的第一绝缘膜; 设置在所述第一绝缘膜上的电荷保持层; 设置在电荷保持层上的第二绝缘膜; 以及包括设置在第二绝缘膜上的第二通道的半导体层，以及设置在第二通道两侧的源极区域和漏极区域。

    Nonvolatile semiconductor memory device and method for driving same
    10.
    发明授权
    Nonvolatile semiconductor memory device and method for driving same 有权

    公开(公告)号：US08391075B2

    公开(公告)日：2013-03-05

    申请号：US13239964

    申请日：2011-09-22

    申请人： Jun Fujiki ,  Naoki Yasuda ,  Koichi Muraoka

    发明人： Jun Fujiki ,  Naoki Yasuda ,  Koichi Muraoka

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching a potential of the gate electrodes with that of the semiconductor layer.