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    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07968956B2

    公开(公告)日：2011-06-28

    申请号：US12388965

    申请日：2009-02-19

    申请人： Kosuke Tatsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

    发明人： Kosuke Tatsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

    IPC分类号： H01L29/78 ,  H01L21/70

    CPC分类号： H01L21/823828 ,  H01L21/823842 ,  H01L29/785

    摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

    摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道 形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。 与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比 的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

    Configuration memory
    4.
    发明授权
    Configuration memory 有权
    配置内存

    公开(公告)号：US08842475B2

    公开(公告)日：2014-09-23

    申请号：US13603666

    申请日：2012-09-05

    申请人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

    发明人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

    IPC分类号： G11C11/34

    CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

    摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

    摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。

    Memory system including key-value store
    5.
    发明授权
    Memory system including key-value store 有权
    内存系统包括键值存储

    公开(公告)号：US09361408B2

    公开(公告)日：2016-06-07

    申请号：US13569605

    申请日：2012-08-08

    申请人： Takao Marukame ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    发明人： Takao Marukame ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    IPC分类号： G06F17/30 ,  G06F12/02

    CPC分类号： G06F17/30982 ,  G06F12/0246 ,  G06F17/30097 ,  G06F17/3012 ,  G06F2212/7201

    摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

    摘要翻译： 根据一个实施例，包括密钥值存储的密钥值存储器的存储器系统包括密钥值数据作为一对密钥和对应于该密钥的值，包括接口，存储器块，地址获取电路和控制器。 接口接收数据写/读请求或基于键值存储的请求。 存储块具有用于存储数据的数据区域和包含键值数据的元数据表。 地址获取电路响应于键的输入而获取地址。 控制器执行存储器块的数据写/读请求，并将获取的地址输出到存储块，并根据键值存储执行请求。 控制器通过接口输出与该键对应的值。

    Memory including transistors with double floating gate structures
    7.
    发明授权
    Memory including transistors with double floating gate structures 失效
    存储器包括具有双浮栅结构的晶体管

    公开(公告)号：US08610196B2

    公开(公告)日：2013-12-17

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    Storage device having full-text search function
    8.
    发明授权
    Storage device having full-text search function 有权
    存储设备具有全文搜索功能

    公开(公告)号：US08321421B2

    公开(公告)日：2012-11-27

    申请号：US12888897

    申请日：2010-09-23

    申请人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

    发明人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

    IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F17/30

    CPC分类号： G06F17/30106 ,  G06F17/30109

    摘要： According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request.

    摘要翻译： 根据一个实施例，存储设备包括接口，第一和第二存储器块以及控制器。 接口接收内容搜索请求。 第一个存储块存储与文件中包含的内容相对应的文件和反转文件。 第二存储器块存储文件搜索表。 控制器为包含在文件中的每个内容创建反转文件，并将包含内容的文件的ID存储在反转文件中。 控制器通过搜索内容，从存储在第一存储器块中的反转文件中获得相应的反转文件，并在文件搜索表中存储所获得的反转文件中包括的文件的ID。 控制器从接口输出存储在文件搜索表中的文件的ID作为内容搜索请求的搜索结果。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09007823B2

    公开(公告)日：2015-04-14

    申请号：US13480853

    申请日：2012-05-25

    申请人： Takahiro Kurita ,  Yoshifumi Nishi ,  Kosuke Tatsumura ,  Atsuhiro Kinoshita

    发明人： Takahiro Kurita ,  Yoshifumi Nishi ,  Kosuke Tatsumura ,  Atsuhiro Kinoshita

    IPC分类号： G11C11/34 ,  H01L21/28 ,  G11C7/02 ,  G11C11/403 ,  H01L29/423 ,  H01L29/51 ,  H01L27/108

    CPC分类号： H01L21/28291 ,  G11C7/02 ,  G11C11/403 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10873 ,  H01L29/4234 ,  H01L29/516

    摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

    摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。

    Circuit having programmable match determination function, and LUT circuit, MUX circuit and FPGA device with such function and method of data writing
    10.
    发明授权
    Circuit having programmable match determination function, and LUT circuit, MUX circuit and FPGA device with such function and method of data writing 有权
    具有可编程匹配确定功能的电路，以及具有数据写入功能和方法的LUT电路，MUX电路和FPGA器件

    公开(公告)号：US08908408B2

    公开(公告)日：2014-12-09

    申请号：US13613701

    申请日：2012-09-13

    申请人： Kosuke Tatsumura ,  Masato Oda ,  Atsuhiro Kinoshita ,  Koichiro Zaitsu ,  Mari Matsumoto ,  Shinichi Yasuda

    发明人： Kosuke Tatsumura ,  Masato Oda ,  Atsuhiro Kinoshita ,  Koichiro Zaitsu ,  Mari Matsumoto ,  Shinichi Yasuda

    IPC分类号： G11C15/00

    CPC分类号： H03K19/17728 ,  G11C15/04 ,  G11C15/046 ,  H03K19/17712

    摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

    摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。