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    PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF 审中-公开
    具有嵌入芯片的包装基板及其制造方法

    公开(公告)号：US20090032930A1

    公开(公告)日：2009-02-05

    申请号：US11832466

    申请日：2007-08-01

    申请人： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Shang-Wei Chen ,  Kan-Jung Chia

    发明人： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Shang-Wei Chen ,  Kan-Jung Chia

    IPC分类号： H01L21/52 ,  H01L23/18

    CPC分类号： H01L21/52 ,  H01L23/24 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/00

    摘要： A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.

    摘要翻译： 具有嵌入其中的芯片的封装基板包括其中具有第一腔的第一铝基板; 第二铝基板，具有对应于第一空腔的第二腔; 设置在所述第一铝基板和所述第二铝基板之间的电介质层; 嵌入在所述第一腔和所述第二腔中的芯片，具有其上具有多个电极焊盘的活性表面; 以及设置在第一铝基板的表面和芯片的有源表面上的一个堆积结构，其中，所述积层结构具有电连接到电极焊盘的多个导电通孔。 通过使用铝或铝合金作为基材的材料，显着减少了基板翘曲。 另外，公开了一种制造具有嵌入其中的芯片的封装衬底的方法。

    Package on package structure
    6.
    发明申请
    Package on package structure 审中-公开
    封装结构封装

    公开(公告)号：US20090102039A1

    公开(公告)日：2009-04-23

    申请号：US12285818

    申请日：2008-10-15

    申请人： Shih-Ping Hsu ,  Kan-Jung Chia ,  Shang-Wei Chen

    发明人： Shih-Ping Hsu ,  Kan-Jung Chia ,  Shang-Wei Chen

    IPC分类号： H01L23/48

    CPC分类号： H01L23/142 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

    摘要： The present invention relates to a package on package (PoP) structure, which comprises: a first packaging substrate having a plurality of conductive elements on its surface; a second packaging substrate having a plurality of conductive elements on its surface; and a surface-ceramic aluminum plate sandwiched between the first packaging substrate and the second packaging substrate. The surface-ceramic aluminum plate includes plural plated through holes extending through the layer. In addition, the first packaging substrate electrically conducts with the second packaging substrate through these plated through holes. The disclosed structure eliminates the warpage problem of PoP structure, and enhances the strength of PoP structure.

    摘要翻译： 本发明涉及封装封装（PoP）结构，其包括：第一封装基板，其表面上具有多个导电元件; 第二包装基板，其表面上具有多个导电元件; 以及夹在第一包装基板和第二包装基板之间的表面陶瓷铝板。 表面陶瓷铝板包括贯穿该层的多个电镀通孔。 此外，第一包装基板通过这些电镀通孔与第二封装基板电连接。 所公开的结构消除了PoP结构的翘曲问题，并提高了PoP结构的强度。

    Package substrate embedded with semiconductor component
    8.
    发明授权
    Package substrate embedded with semiconductor component 有权
    封装衬底嵌入半导体元件

    公开(公告)号：US08058718B2

    公开(公告)日：2011-11-15

    申请号：US12340405

    申请日：2008-12-19

    申请人： Shih-Ping Hsu ,  Kan-Jung Chia

    发明人： Shih-Ping Hsu ,  Kan-Jung Chia

    IPC分类号： H01L23/24

    CPC分类号： H01L24/19 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/18162

    摘要： A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias. The first conductive vias are disposed in the openings of the dielectric and passivation layers and the first circuit layer is electrically connected to the electrode pads, thereby allowing the first conductive vias to be electrically connected to the electrode pads of the chip.

    摘要翻译： 嵌入半导体部件的封装基板包括基板，半导体芯片，第一介电层，第一电路层和第一导电孔。 基板形成有用于使半导体芯片固定在其中的开口。 半导体芯片具有活性表面和非活性表面，其中在其有效表面上形成多个电极焊盘，并且在其上设置钝化层。 第一电介质层设置在衬底和钝化层上，其中通孔形成在与电极焊盘相对应的位置处，并且穿透电介质层和钝化层以暴露电极焊盘。 第一电路层设置在第一电介质层上并电连接到第一导电通孔。 第一导电通孔设置在介电层和钝化层的开口中，并且第一电路层电连接到电极焊盘，从而允许第一导电通孔电连接到芯片的电极焊盘。

    PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT
    10.
    发明申请
    PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT 审中-公开
    封装衬底嵌入半导体元件

    公开(公告)号：US20090168380A1

    公开(公告)日：2009-07-02

    申请号：US12340445

    申请日：2008-12-19

    申请人： Shih-Ping Hsu ,  Kan-Jung Chia

    发明人： Shih-Ping Hsu ,  Kan-Jung Chia

    IPC分类号： H05K1/18

    CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/18162 ,  H05K3/4644 ,  H05K2201/10674 ,  H05K2203/072 ,  H05K2203/1469

    摘要： A package substrate embedded with a semiconductor component is provided. A semiconductor chip is received in a cavity of a substrate body, and has electrode pads on an active surface thereof. A passivation layer is disposed on the active surface and has openings for exposing the electrode pads. An electroless plating metal layer, a first sputtering metal layer and a second sputtering metal layer are sequentially formed on the electrode pads, the openings of the passivation layer and the passivation layer surface around the openings. Contact pads are formed on the second sputtering metal layer. A first dielectric layer is disposed on the substrate body and the passivation layer. A first circuit layer is formed on the first dielectric layer. First conductive vias are formed in the first dielectric layer and electrically connected to the contact pads. The first circuit layer is electrically connected to the first conductive vias.

    摘要翻译： 提供了嵌入半导体部件的封装基板。 半导体芯片被接收在基板主体的空腔中，并且在其有效表面上具有电极焊盘。 钝化层设置在有源表面上并具有用于暴露电极焊盘的开口。 在电极焊盘，钝化层的开口和开口周围的钝化层表面上依次形成化学镀金属层，第一溅射金属层和第二溅射金属层。 接触焊盘形成在第二溅射金属层上。 第一电介质层设置在衬底主体和钝化层上。 在第一电介质层上形成第一电路层。 第一导电通孔形成在第一电介质层中并电连接到接触焊盘。 第一电路层电连接到第一导电通孔。