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12 条记录 (耗时 0.018 秒)

    Method for producing a low defect layer of silicon-on-sapphire wafer
    1.
    发明授权
    Method for producing a low defect layer of silicon-on-sapphire wafer 失效
    用于制造蓝宝石蓝宝石晶片的低缺陷层的方法

    公开(公告)号：US4177084A

    公开(公告)日：1979-12-04

    申请号：US913982

    申请日：1978-06-09

    申请人： Silvanus S. Lau ,  James W. Mayer ,  Thomas W. Sigmon

    发明人： Silvanus S. Lau ,  James W. Mayer ,  Thomas W. Sigmon

    IPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  C30B29/20 ,  C30B33/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/265 ,  H01L21/324 ,  H01L21/86 ,  H01L27/12 ,  H01L7/00

    CPC分类号： C30B29/06 ,  C30B25/18 ,  C30B33/00 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/324 ,  Y10S148/048 ,  Y10S148/077 ,  Y10S148/093 ,  Y10S438/967

    摘要： A method is provided for producing a low-defect layer of silicon on a sapphire substrate. A silicon-on-sapphire (SOS) wafer is formed by initially epitaxially depositing silicon on the sapphire substrate to form a monocrystalline layer which is substantially free of lattice defects near its surface, but which exhibits a high defect density near the sapphire substrate. The wafer is subsequently subjected to an ion implantation to form an amorphous region in the silicon near the silicon-sapphire interface. The implanted ions are preferably "channeled" through the silicon layer to insure that the amorphous region will be localized in the imperfect region near the substrate, leaving the upper region of the silicon layer undamaged. During a subsequent high temperature anneal cycle, monocrystalline silicon is regrown from the residual upper regions of the silicon down to the silicon-sapphire interface, producing a silicon layer having a greatly reduced defect density throughout the layer.

    摘要翻译： 提供了一种在蓝宝石衬底上制造低缺陷硅层的方法。 通过最初在蓝宝石衬底上外延地沉积硅以形成在其表面附近基本上没有晶格缺陷但在蓝宝石衬底附近表现出高缺陷密度的单晶层，形成硅蓝宝石（SOS）晶片。 接着对晶片进行离子注入，以在硅 - 蓝宝石界面附近的硅中形成非晶区域。 注入的离子优选通过硅层“引导”，以确保非晶区域将局限于衬底附近的不完美区域，使得硅层的上部区域不受损害。 在随后的高温退火循环中，将单晶硅从硅的残余上部区域重新生长到硅 - 蓝宝石界面，从而产生在整个层中具有大大降低的缺陷密度的硅层。

    Self-aligned process for capping copper lines
    3.
    发明授权
    Self-aligned process for capping copper lines 失效
    自动对线加工铜线

    公开(公告)号：US5447599A

    公开(公告)日：1995-09-05

    申请号：US257303

    申请日：1994-06-09

    申请人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    发明人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    IPC分类号： H01L21/768 ,  H01L23/532 ,  C23C10/00 ,  C23F1/00 ,  H01L21/00

    CPC分类号： H01L21/76858 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/238 ,  Y10T428/239 ,  Y10T428/24917

    摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.

    摘要翻译： 本发明的特征在于制造铜基多层互连的工艺和所得到的制品。 由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。 铜线约为1微米厚。 线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。 对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。 然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。 剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内 约五分钟。 因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。 作为扩散阻挡层，TiN（O）层比TiN更有效。

    Processing of hydroxylapatite coatings on titanium alloy bone prostheses
    6.
    发明授权
    Processing of hydroxylapatite coatings on titanium alloy bone prostheses 失效
    钛合金骨假体羟基磷灰石涂层的加工

    公开(公告)号：US5817326A

    公开(公告)日：1998-10-06

    申请号：US566339

    申请日：1995-12-01

    申请人： Michael A. Nastasi ,  Timothy E. Levine ,  James W. Mayer ,  Vincent B. Pizziconi

    发明人： Michael A. Nastasi ,  Timothy E. Levine ,  James W. Mayer ,  Vincent B. Pizziconi

    IPC分类号： A61F2/00 ,  A61F2/30 ,  A61L27/32 ,  C23C14/48 ,  A61F2/28

    CPC分类号： A61L27/32 ,  A61F2/30767 ,  C23C14/48 ,  A61F2/3094 ,  A61F2310/00023 ,  A61F2310/00796

    摘要： Processing of hydroxylapatite sol-gel films on titanium alloy bone prostheses. A method utilizing non-line-of-sight ion beam implantation and/or rapid thermal processing to provide improved bonding of layers of hydroxylapatite to titanium alloy substrates while encouraging bone ingrowth into the hydroxylapatite layers located away from the substrate, is described for the fabrication of prostheses. The first layer of hydroxylapatite is mixed into the substrate by the ions or rapidly thermally annealed, while subsequent layers are heat treated or densified using ion implantation to form layers of decreasing density and larger crystallization, with the outermost layers being suitable for bone ingrowth.

    摘要翻译： 在钛合金骨假体上加工羟基磷灰石溶胶 - 凝胶膜。 描述了一种使用非视距离离子束注入和/或快速热处理来提供羟基磷灰石层与钛合金基底的改进结合，同时鼓励骨向内生长到位于远离基底的羟基磷灰石层中的方法，用于制造 的假肢。 羟基磷灰石的第一层通过离子混合到衬底中或快速热退火，而随后的层通过离子注入进行热处理或致密化，以形成密度降低和结晶较大的层，最外层适用于骨向内生长。

    Microwave-Induced Ion Cleaving and Patternless Transfer of Semiconductor Films
    7.
    发明申请
    Microwave-Induced Ion Cleaving and Patternless Transfer of Semiconductor Films 审中-公开
    微波诱导离子切割和无模式转移半导体薄膜

    公开(公告)号：US20100112780A1

    公开(公告)日：2010-05-06

    申请号：US11995295

    申请日：2006-07-11

    申请人： Douglas C. Thompson ,  James W. Mayer ,  Michael Nastasi ,  Terry L. Alford

    发明人： Douglas C. Thompson ,  James W. Mayer ,  Michael Nastasi ,  Terry L. Alford

    IPC分类号： H01L21/18

    CPC分类号： H01L21/76254

    摘要： A method of ion cleaving using microwave radiation is described. The method includes using microwave radiation to induce exfoliation of a semiconductor layer from a donor substrate. The donor substrate may be implanted, bonded to a carrier substrate, and heated via the microwave radiation. The implanted portion of the donor substrate may include increased damage and/or dipoles (relative to non-implanted portions of the donor substrate), which more readily absorb microwave radiation. Consequently, by using microwave radiation, an exfoliation time may be reduced to 12 seconds or less. In addition, a presented method also includes the use of focused ion beam implantation to achieve a pattern-less transfer of a semiconductor layer onto a carrier substrate.

    摘要翻译： 描述了使用微波辐射的离子切割的方法。 该方法包括使用微波辐射来从施主衬底诱导半导体层的剥离。 可以将施主衬底注入，结合到载体衬底上，并通过微波辐射加热。 供体衬底的植入部分可以包括更容易吸收微波辐射的增加的损伤和/或偶极（相对于供体衬底的非植入部分）。 因此，通过使用微波辐射，剥离时间可以减少到12秒以下。 此外，所提出的方法还包括使用聚焦离子束注入来实现半导体层到载体衬底上的无模式转移。

    Direct patterning of nanometer-scale silicide structures on silicon by ion-beam implantation through a thin barrier layer
    8.
    发明授权
    Direct patterning of nanometer-scale silicide structures on silicon by ion-beam implantation through a thin barrier layer 失效
    通过离子束注入通过薄的阻挡层直接图案化硅上的纳米级硅化物结构

    公开(公告)号：US06750124B1

    公开(公告)日：2004-06-15

    申请号：US10071756

    申请日：2002-02-06

    申请人： Martin Mitan ,  David P. Pivin, Jr. ,  James W. Mayer ,  Terry L. Alford

    发明人： Martin Mitan ,  David P. Pivin, Jr. ,  James W. Mayer ,  Terry L. Alford

    IPC分类号： H01L2144

    CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652

    摘要： Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

    摘要翻译： 给出直接聚焦离子束（FIB）混合作为在硅表面上图形化金属硅化物结构的方法。 该技术允许制造亚微米结构而不使用基于抗蚀剂的光刻方法。 可以通过该方法制备包含金属硅化物连接的VLSI，互连和结构。 导致具有良好的电路速度和减小的RC时间延迟的快速半导体器件包括MEMS，MOSFET，CMOS，pMOS，nMOS和BiCMOS等技术。

    Self-aligned process for capping copper lines
    9.
    发明授权
    Self-aligned process for capping copper lines 失效
    自动对线加工铜线

    公开(公告)号：US5310602A

    公开(公告)日：1994-05-10

    申请号：US960627

    申请日：1992-10-13

    申请人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    发明人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76858 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/238 ,  Y10T428/239 ,  Y10T428/24917

    摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.

    摘要翻译： 本发明的特征在于制造铜基多层互连的工艺和所得到的制品。 由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。 铜线约为1微米厚。 线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。 对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。 然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。 剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内 约五分钟。 因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。 作为扩散阻挡层，TiN（O）层比TiN更有效。

    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits
    10.
    发明授权
    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits 失效
    在超大规模集成（ULSI）电路中制造铜互连的工艺

    公开(公告)号：US5277985A

    公开(公告)日：1994-01-11

    申请号：US790971

    申请日：1991-11-12

    申请人： Jian Li ,  Evan Colgan ,  James W. Mayer

    发明人： Jian Li ,  Evan Colgan ,  James W. Mayer

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24917

    摘要： The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

    摘要翻译： 本发明在超大规模集成（ULSI）电路的硅衬底上具有低温，自封装的铜互连线。 互连线是包括以下步骤的工艺的产物：（a）将铜与约10原子量的钛的钛合金化; （b）将铜/钛合金层沉积在ULSI电路的二氧化硅/硅衬底上; （c）图案化铜/钛层以在衬底上形成互连线; （d）通过铜/钛互连线以60摄氏度到80摄氏度/分钟的近似斜率的快速加热在铜互连线上形成富钛表面膜; 并且（e）在氨气气氛中在约450至650℃的近似范围内的低温下将互连线的富钛表面渗氮约15至40分钟，以形成围绕所述铜的氮化钛封装层 互连线。